1 /**************************************************************************/
2 /* File: ems_cpcpci.c - support for EMS-WUENSCHE CPC-PCI card */
4 /* LinCAN - (Not only) Linux CAN bus driver */
5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
7 /* Copyright (C) 2004 Paolo Grisleri <grisleri@ce.unipr.it> */
8 /* Funded by OCERA and FRESCOR IST projects */
9 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
11 /* LinCAN is free software; you can redistribute it and/or modify it */
12 /* under terms of the GNU General Public License as published by the */
13 /* Free Software Foundation; either version 2, or (at your option) any */
14 /* later version. LinCAN is distributed in the hope that it will be */
15 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
16 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
17 /* General Public License for more details. You should have received a */
18 /* copy of the GNU General Public License along with LinCAN; see file */
19 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
20 /* Cambridge, MA 02139, USA. */
22 /* To allow use of LinCAN in the compact embedded systems firmware */
23 /* and RT-executives (RTEMS for example), main authors agree with next */
24 /* special exception: */
26 /* Including LinCAN header files in a file, instantiating LinCAN generics */
27 /* or templates, or linking other files with LinCAN objects to produce */
28 /* an application image/executable, does not by itself cause the */
29 /* resulting application image/executable to be covered by */
30 /* the GNU General Public License. */
31 /* This exception does not however invalidate any other reasons */
32 /* why the executable file might be covered by the GNU Public License. */
33 /* Publication of enhanced or derived LinCAN files is required although. */
34 /**************************************************************************/
36 #include "../include/can.h"
37 #include "../include/can_sysdep.h"
38 #include "../include/main.h"
39 #include "../include/sja1000p.h"
41 #ifdef CAN_ENABLE_PCI_SUPPORT
44 /* the only one supported: EMS CPC-PCI */
45 // PGX: check identifiers name
46 # define EMS_CPCPCI_PCICAN_VENDOR 0x110a
47 # define EMS_CPCPCI_PCICAN_ID 0x2104
49 /*The Infineon PSB4610 PITA-2 is used as PCI to local bus bridge*/
50 /*BAR0 - MEM - bridge control registers*/
52 /*BAR1 - MEM - parallel interface*/
53 /* 0 more EMS control registers
54 * 0x400 the first SJA1000
55 * 0x600 the second SJA1000
56 * each register occupies 4 bytes
59 /*PSB4610 PITA-2 bridge control registers*/
60 #define PITA2_ICR 0x00 /* Interrupt Control Register */
61 #define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
62 #define PITA2_ICR_GP0_INT 0x00000004 /* [RC] GP0 Interrupt */
63 /* GP0_Int_En=1, GP0_Out_En=0 and low detected */
64 #define PITA2_ICR_GP1_INT 0x00000008 /* [RC] GP1 Interrupt */
65 #define PITA2_ICR_GP2_INT 0x00000010 /* [RC] GP2 Interrupt */
66 #define PITA2_ICR_GP3_INT 0x00000020 /* [RC] GP2 Interrupt */
67 #define PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
69 #define PITA2_MISC 0x1C /* Miscellaneous Register */
70 #define PITA2_MISC_CONFIG 0x04000000
71 /* Multiplexed Parallel_interface_mode */
73 #define EMS_CPCPCI_BYTES_PER_CIRCUIT 0x200
74 /* Each CPC register occupies 4 bytes */
75 #define EMS_CPCPCI_BYTES_PER_REG 0x4
77 // Standard value: Pushpull (OCTP1|OCTN1|OCTP0|OCTN0|OCM1)
78 #define EMS_CPCPCI_OCR_DEFAULT_STD 0xDA
79 // For Galathea piggyback.
80 #define EMS_CPCPCI_OCR_DEFAULT_GAL 0xDB
84 The board configuration is probably following:
85 " RX1 is connected to ground.
86 " TX1 is not connected.
87 " CLKO is not connected.
88 " Setting the OCR register to 0xDA is a good idea.
89 This means normal output mode , push-pull and the correct polarity.
90 " In the CDR register, you should set CBP to 1.
91 You will probably also want to set the clock divider value to 7
92 (meaning direct oscillator output) because the second SJA1000 chip
93 is driven by the first one CLKOUT output.
99 void ems_cpcpci_disconnect_irq(struct candevice_t *candev)
101 /* Disable interrupts from card */
102 can_writel(0, candev->aux_base_addr + PITA2_ICR);
105 void ems_cpcpci_connect_irq(struct candevice_t *candev)
107 /* Enable interrupts from card */
108 can_writel(PITA2_ICR_INT0_En, candev->aux_base_addr + PITA2_ICR);
112 int ems_cpcpci_request_io(struct candevice_t *candev)
114 unsigned long pita2_addr;
115 unsigned long io_addr;
118 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
119 if(pci_request_region(candev->sysdevptr.pcidev, 0, "ems_cpcpci_pita2") != 0){
120 CANMSG("Request of ems_cpcpci_pita2 range failed\n");
122 }else if(pci_request_region(candev->sysdevptr.pcidev, 1, "ems_cpcpci_io") != 0){
123 CANMSG("Request of ems_cpcpci_io range failed\n");
126 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
127 if(pci_request_regions(candev->sysdevptr.pcidev, "EMS_CPCPCI") != 0){
128 CANMSG("Request of ems_cpcpci_s5920 regions failed\n");
131 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
133 pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
134 if (!(candev->aux_base_addr = ioremap(pita2_addr,
135 pci_resource_len(candev->sysdevptr.pcidev,0)))) {
136 CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
137 goto error_ioremap_pita2;
140 io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
141 if (!(candev->dev_base_addr = ioremap(io_addr,
142 pci_resource_len(candev->sysdevptr.pcidev,1)))) {
143 CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
144 goto error_ioremap_io;
147 candev->io_addr=io_addr;
148 candev->res_addr=pita2_addr;
151 * this is redundant with chip initialization, but remap address
152 * can change when resources are temporarily released
154 for(i=0;i<candev->nr_all_chips;i++) {
155 struct canchip_t *chip=candev->chip[i];
157 chip->chip_base_addr = candev->dev_base_addr+
158 0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
159 if(!chip->msgobj[0]) continue;
160 chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
163 /* Configure PITA-2 parallel interface */
164 can_writel(PITA2_MISC_CONFIG, candev->aux_base_addr + PITA2_MISC);
166 ems_cpcpci_disconnect_irq(candev);
171 iounmap(candev->aux_base_addr);
173 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
174 pci_release_region(candev->sysdevptr.pcidev, 1);
176 pci_release_region(candev->sysdevptr.pcidev, 0);
177 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
178 pci_release_regions(candev->sysdevptr.pcidev);
179 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
184 int ems_cpcpci_release_io(struct candevice_t *candev)
186 ems_cpcpci_disconnect_irq(candev);
188 iounmap(candev->dev_base_addr);
189 iounmap(candev->aux_base_addr);
190 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
191 pci_release_region(candev->sysdevptr.pcidev, 1);
192 pci_release_region(candev->sysdevptr.pcidev, 0);
193 #else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
194 pci_release_regions(candev->sysdevptr.pcidev);
195 #endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
201 void ems_cpcpci_write_register(unsigned data, can_ioptr_t address)
203 address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
204 *(EMS_CPCPCI_BYTES_PER_REG-1));
205 can_writeb(data,address);
208 unsigned ems_cpcpci_read_register(can_ioptr_t address)
210 address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
211 *(EMS_CPCPCI_BYTES_PER_REG-1));
212 return can_readb(address);
215 int ems_cpcpci_irq_handler(int irq, struct canchip_t *chip)
217 //struct canchip_t *chip=(struct canchip_t *)dev_id;
218 struct candevice_t *candev=chip->hostdevice;
223 icr=can_readl(candev->aux_base_addr + PITA2_ICR);
224 if(!(icr & PITA2_ICR_INT0)) return CANCHIP_IRQ_NONE;
226 /* correct way to handle interrupts from all chips connected to the one PITA-2 */
228 can_writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->aux_base_addr + PITA2_ICR);
230 for(i=0;i<candev->nr_all_chips;i++){
231 chip=candev->chip[i];
232 if(!chip || !(chip->flags&CHIP_CONFIGURED))
234 if(sja1000p_irq_handler(irq, chip))
237 icr=can_readl(candev->aux_base_addr + PITA2_ICR);
238 } while((icr & PITA2_ICR_INT0)||test_irq_again);
239 return CANCHIP_IRQ_HANDLED;
242 int ems_cpcpci_reset(struct candevice_t *candev)
245 struct canchip_t *chip;
248 DEBUGMSG("Resetting EMS_CPCPCI hardware ...\n");
250 /* Assert PTADR# - we're in passive mode so the other bits are not important */
252 ems_cpcpci_disconnect_irq(candev);
254 for(chip_nr=0;chip_nr<candev->nr_all_chips;chip_nr++){
255 if(!candev->chip[chip_nr]) continue;
256 chip=candev->chip[chip_nr];
258 ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
261 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
262 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
264 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
267 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
268 while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
269 if(!i--) return -ENODEV;
271 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
274 cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
275 ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
277 ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
279 ems_cpcpci_read_register(chip->chip_base_addr+SJAIR);
283 ems_cpcpci_connect_irq(candev);
288 int ems_cpcpci_init_hw_data(struct candevice_t *candev)
290 struct pci_dev *pcidev;
294 pcidev = can_pci_get_next_untaken_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID);
298 if (pci_enable_device (pcidev)){
299 printk(KERN_CRIT "Setup of EMS_CPCPCI failed\n");
300 can_pci_dev_put(pcidev);
303 candev->sysdevptr.pcidev=pcidev;
306 if(!(pci_resource_flags(pcidev,0)&IORESOURCE_MEM)){
307 printk(KERN_CRIT "EMS_CPCPCI region %d is not memory\n",i);
308 can_pci_dev_put(pcidev);
313 /*request IO access temporarily to check card presence*/
314 if(ems_cpcpci_request_io(candev)<0) {
315 can_pci_dev_put(pcidev);
319 /*** candev->aux_base_addr=pci_resource_start(pcidev,0); ***/
320 /* some control registers */
321 /*** candev->dev_base_addr=pci_resource_start(pcidev,1); ***/
322 /* 0 more EMS control registers
323 * 0x400 the first SJA1000
324 * 0x600 the second SJA1000
325 * each register occupies 4 bytes
328 /*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
330 for(l=0,i=0;i<4;i++){
332 l|=can_readb(candev->dev_base_addr + i*4);
334 i=can_readb(candev->dev_base_addr + i*5);
336 CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
339 CANMSG("EMS CPC-PCI unexpected check values\n");
342 /*if (!strcmp(candev->hwname,"ems_cpcpci"))*/
343 candev->nr_82527_chips=0;
344 candev->nr_sja1000_chips=2;
345 candev->nr_all_chips=2;
347 ems_cpcpci_release_io(candev);
352 void ems_cpcpci_done_hw_data(struct candevice_t *candev)
354 struct pci_dev *pcidev = candev->sysdevptr.pcidev;
355 can_pci_dev_put(pcidev);
358 int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr)
360 if(candev->sysdevptr.pcidev==NULL)
363 /* initialize common routines for the SJA1000 chip */
364 sja1000p_fill_chipspecops(candev->chip[chipnr]);
366 /* special version of the IRQ handler is required for CPC-PCI board */
367 candev->chip[chipnr]->chipspecops->irq_handler=ems_cpcpci_irq_handler;
369 candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
371 candev->chip[chipnr]->chip_base_addr = candev->dev_base_addr+
372 0x400 + chipnr*EMS_CPCPCI_BYTES_PER_CIRCUIT;
373 candev->chip[chipnr]->flags = 0;
374 candev->chip[chipnr]->int_cpu_reg = 0;
375 candev->chip[chipnr]->int_clk_reg = 0;
376 candev->chip[chipnr]->int_bus_reg = 0;
377 /* CLKOUT has to be equal to oscillator frequency to drive second chip */
378 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | 7;
379 candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD;
380 candev->chip[chipnr]->clock = 16000000;
381 candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
386 int ems_cpcpci_init_obj_data(struct canchip_t *chip, int objnr)
388 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
392 int ems_cpcpci_program_irq(struct candevice_t *candev)
398 int ems_cpcpci_register(struct hwspecops_t *hwspecops)
400 hwspecops->request_io = ems_cpcpci_request_io;
401 hwspecops->release_io = ems_cpcpci_release_io;
402 hwspecops->reset = ems_cpcpci_reset;
403 hwspecops->init_hw_data = ems_cpcpci_init_hw_data;
404 hwspecops->done_hw_data = ems_cpcpci_done_hw_data;
405 hwspecops->init_chip_data = ems_cpcpci_init_chip_data;
406 hwspecops->init_obj_data = ems_cpcpci_init_obj_data;
407 hwspecops->write_register = ems_cpcpci_write_register;
408 hwspecops->read_register = ems_cpcpci_read_register;
409 hwspecops->program_irq = ems_cpcpci_program_irq;
414 #endif /*CAN_ENABLE_PCI_SUPPORT*/