1 /******************************************************************************
6 * Header file for Philips LPC ARM Processors.
7 * Copyright 2004 R O SoftWare
9 * No guarantees, warrantees, or promises, implied or otherwise.
10 * May be used for hobby or commercial purposes provided copyright
11 * notice remains intact.
13 *****************************************************************************/
17 // Timer & PWM Registers
20 REG32 ir; // Interrupt Register
21 REG32 tcr; // Timer Control Register
22 REG32 tc; // Timer Counter
23 REG32 pr; // Prescale Register
24 REG32 pc; // Prescale Counter Register
25 REG32 mcr; // Match Control Register
26 REG32 mr0; // Match Register 0
27 REG32 mr1; // Match Register 1
28 REG32 mr2; // Match Register 2
29 REG32 mr3; // Match Register 3
30 REG32 ccr; // Capture Control Register
31 REG32 cr0; // Capture Register 0
32 REG32 cr1; // Capture Register 1
33 REG32 cr2; // Capture Register 2
34 REG32 cr3; // Capture Register 3
35 REG32 emr; // External Match Register
36 REG32 mr4; // Match Register 4
37 REG32 mr5; // Match Register 5
38 REG32 mr6; // Match Register 6
39 REG32 pcr; // Control Register
40 REG32 ler; // Latch Enable Register
43 // Timer Interrupt Register Bit Definitions
44 #define TIR_MR0I (1 << 0) // Interrupt flag for match channel 0
45 #define TIR_MR1I (1 << 1) // Interrupt flag for match channel 1
46 #define TIR_MR2I (1 << 2) // Interrupt flag for match channel 2
47 #define TIR_MR3I (1 << 3) // Interrupt flag for match channel 3
48 #define TIR_CR0I (1 << 4) // Interrupt flag for capture channel 0 event
49 #define TIR_CR1I (1 << 5) // Interrupt flag for capture channel 1 event
50 #define TIR_CR2I (1 << 6) // Interrupt flag for capture channel 2 event
51 #define TIR_CR3I (1 << 7) // Interrupt flag for capture channel 3 event
53 // PWM Interrupt Register Bit Definitions
54 #define PWMIR_MR0I (1 << 0) // Interrupt flag for match channel 0
55 #define PWMIR_MR1I (1 << 1) // Interrupt flag for match channel 1
56 #define PWMIR_MR2I (1 << 2) // Interrupt flag for match channel 2
57 #define PWMIR_MR3I (1 << 3) // Interrupt flag for match channel 3
58 #define PWMIR_MR4I (1 << 8) // Interrupt flag for match channel 4
59 #define PWMIR_MR5I (1 << 9) // Interrupt flag for match channel 5
60 #define PWMIR_MR6I (1 << 10) // Interrupt flag for match channel 6
61 #define PWMIR_MASK (0x070F)
63 // Timer Control Register Bit Definitions
64 #define TCR_ENABLE (1 << 0)
65 #define TCR_RESET (1 << 1)
67 // PWM Control Register Bit Definitions
68 #define PWMCR_ENABLE (1 << 0)
69 #define PWMCR_RESET (1 << 1)
71 // PWM Latch Enable Register Bit Definitions
72 #define PWMLER_PWML0E (1<<0)
73 #define PWMLER_PWML1E (1<<1)
74 #define PWMLER_PWML2E (1<<2)
75 #define PWMLER_PWML3E (1<<3)
76 #define PWMLER_PWML4E (1<<4)
77 #define PWMLER_PWML5E (1<<5)
78 #define PWMLER_PWML6E (1<<6)
80 // Timer Match Control Register Bit Definitions
81 #define TMCR_MR0_I (1 << 0) // Enable Interrupt when MR0 matches TC
82 #define TMCR_MR0_R (1 << 1) // Enable Reset of TC upon MR0 match
83 #define TMCR_MR0_S (1 << 2) // Enable Stop of TC upon MR0 match
84 #define TMCR_MR1_I (1 << 3) // Enable Interrupt when MR1 matches TC
85 #define TMCR_MR1_R (1 << 4) // Enable Reset of TC upon MR1 match
86 #define TMCR_MR1_S (1 << 5) // Enable Stop of TC upon MR1 match
87 #define TMCR_MR2_I (1 << 6) // Enable Interrupt when MR2 matches TC
88 #define TMCR_MR2_R (1 << 7) // Enable Reset of TC upon MR2 match
89 #define TMCR_MR2_S (1 << 8) // Enable Stop of TC upon MR2 match
90 #define TMCR_MR3_I (1 << 9) // Enable Interrupt when MR3 matches TC
91 #define TMCR_MR3_R (1 << 10) // Enable Reset of TC upon MR3 match
92 #define TMCR_MR3_S (1 << 11) // Enable Stop of TC upon MR3 match
94 // Timer Capture Control Register Bit Definitions
95 #define TCCR_CR0_R (1 << 0) // Enable Rising edge on CAPn.0 will load TC to CR0
96 #define TCCR_CR0_F (1 << 1) // Enable Falling edge on CAPn.0 will load TC to CR0
97 #define TCCR_CR0_I (1 << 2) // Enable Interrupt on load of CR0
98 #define TCCR_CR1_R (1 << 3) // Enable Rising edge on CAPn.1 will load TC to CR1
99 #define TCCR_CR1_F (1 << 4) // Enable Falling edge on CAPn.1 will load TC to CR1
100 #define TCCR_CR1_I (1 << 5) // Enable Interrupt on load of CR1
101 #define TCCR_CR2_R (1 << 6) // Enable Rising edge on CAPn.2 will load TC to CR2
102 #define TCCR_CR2_F (1 << 7) // Enable Falling edge on CAPn.2 will load TC to CR2
103 #define TCCR_CR2_I (1 << 8) // Enable Interrupt on load of CR2
104 #define TCCR_CR3_R (1 << 9) // Enable Rising edge on CAPn.3 will load TC to CR3
105 #define TCCR_CR3_F (1 << 10) // Enable Falling edge on CAPn.3 will load TC to CR3
106 #define TCCR_CR3_I (1 << 11) // Enable Interrupt on load of CR3