2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 #include <linux/autoconf.h>
12 #include <linux/ioport.h>
13 #include <linux/delay.h>
14 #include <asm/errno.h>
18 #include "../include/main.h"
19 #include "../include/pccan.h"
20 #include "../include/i82527.h"
21 #include "../include/sja1000.h"
23 int pccanf_request_io(struct candevice_t *candev)
25 if (!can_request_io_region(candev->io_addr+0x4000,0x20,DEVICE_NAME)) {
26 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x4000);
29 else if (!can_request_io_region(candev->io_addr+0x6000,0x04,DEVICE_NAME)) {
30 can_release_io_region(candev->io_addr+0x4000,0x20);
31 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x6000);
35 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x4000, candev->io_addr+0x4000+0x20-1);
36 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x6000, candev->io_addr+0x6000+0x04-1);
41 int pccand_request_io(struct candevice_t *candev)
43 if (pccanf_request_io(candev))
46 if (!can_request_io_region(candev->io_addr+0x5000,0x20,DEVICE_NAME)) {
47 pccanf_release_io(candev);
48 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x5000);
52 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x5000, candev->io_addr+0x5000+0x20-1);
57 int pccanq_request_io(struct candevice_t *candev)
59 unsigned long io_addr;
62 if (pccand_request_io(candev))
65 for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
66 if (!can_request_io_region(io_addr,0x40,DEVICE_NAME)) {
67 CANMSG("Unable to open port: 0x%lx\n",io_addr);
70 can_release_io_region(io_addr,0x40);
72 pccand_release_io(candev);
75 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, io_addr+0x40-1);
80 int pccanf_release_io(struct candevice_t *candev)
82 can_release_io_region(candev->io_addr+0x4000,0x20);
83 can_release_io_region(candev->io_addr+0x6000,0x04);
88 int pccand_release_io(struct candevice_t *candev)
90 pccanf_release_io(candev);
91 can_release_io_region(candev->io_addr+0x5000,0x20);
96 int pccanq_release_io(struct candevice_t *candev)
98 unsigned long io_addr;
101 pccand_release_io(candev);
103 for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
104 can_release_io_region(io_addr,0x40);
110 int pccanf_reset(struct candevice_t *candev)
114 DEBUGMSG("Resetting pccanf/s hardware ...\n");
115 while (i < 1000000) {
117 outb(0x00,candev->res_addr);
119 outb(0x01,candev->res_addr);
120 outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
122 /* Check hardware reset status */
124 while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & CR_RR)
130 CANMSG("Reset status timeout!\n");
131 CANMSG("Please check your hardware.\n");
135 DEBUGMSG("Chip[0] reset status ok.\n");
140 int pccand_reset(struct candevice_t *candev)
144 DEBUGMSG("Resetting pccan-d hardware ...\n");
145 while (i < 1000000) {
147 outb(0x00,candev->res_addr);
149 outb(0x01,candev->res_addr);
150 outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
151 outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
153 /* Check hardware reset status */
155 for (chip_nr=0; chip_nr<2; chip_nr++) {
157 while ( (inb(candev->chip[chip_nr]->chip_base_addr +
158 SJACR) & CR_RR) && (i<=15) ) {
163 CANMSG("Reset status timeout!\n");
164 CANMSG("Please check your hardware.\n");
168 DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
173 int pccanq_reset(struct candevice_t *candev)
178 disable_irq(candev->chip[i]->chip_irq);
180 DEBUGMSG("Resetting pccan-q hardware ...\n");
183 outb(0x00,candev->res_addr);
185 outb_p(0x01,candev->res_addr);
187 outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
188 outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
190 /* Check hardware reset status */
191 for (chip_nr=0; chip_nr<2; chip_nr++) {
193 while( (inb(candev->chip[chip_nr]->chip_base_addr +
194 iCPU) & iCPU_RST) && (i<=15) ) {
199 CANMSG("Reset status timeout!\n");
200 CANMSG("Please check your hardware.\n");
204 DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
206 for (chip_nr=2; chip_nr<4; chip_nr++) {
208 while( (inb(candev->chip[chip_nr]->chip_base_addr +
209 SJACR) & CR_RR) && (i<=15) ) {
214 CANMSG("Reset status timeout!\n");
215 CANMSG("Please check your hardware.\n");
219 DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
223 enable_irq(candev->chip[i]->chip_irq);
228 int pccan_init_hw_data(struct candevice_t *candev)
230 candev->res_addr=candev->io_addr+0x6001;
231 candev->flags |= PROGRAMMABLE_IRQ;
233 if (!strcmp(candev->hwname,"pccan-q")) {
234 candev->nr_82527_chips=2;
235 candev->nr_sja1000_chips=2;
236 candev->nr_all_chips=4;
238 if (!strcmp(candev->hwname,"pccan-f") |
239 !strcmp(candev->hwname,"pccan-s")) {
240 candev->nr_82527_chips=0;
241 candev->nr_sja1000_chips=1;
242 candev->nr_all_chips=1;
244 if (!strcmp(candev->hwname,"pccan-d")) {
245 candev->nr_82527_chips=0;
246 candev->nr_sja1000_chips=2;
247 candev->nr_all_chips=2;
253 int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
255 if (!strcmp(candev->hwname,"pccan-q")) {
257 candev->chip[chipnr]->chip_type="i82527";
258 candev->chip[chipnr]->flags = CHIP_SEGMENTED;
259 candev->chip[chipnr]->int_cpu_reg=iCPU_DSC;
260 candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
261 candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
262 candev->chip[chipnr]->sja_cdr_reg = 0;
263 candev->chip[chipnr]->sja_ocr_reg = 0;
266 candev->chip[chipnr]->chip_type="sja1000";
267 candev->chip[chipnr]->flags = 0;
268 candev->chip[chipnr]->int_cpu_reg = 0;
269 candev->chip[chipnr]->int_clk_reg = 0;
270 candev->chip[chipnr]->int_bus_reg = 0;
271 candev->chip[chipnr]->sja_cdr_reg =
273 candev->chip[chipnr]->sja_ocr_reg =
274 OCR_MODE_NORMAL | OCR_TX0_LH;
276 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
279 candev->chip[chipnr]->chip_type="sja1000";
280 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr;
281 candev->chip[chipnr]->flags = 0;
282 candev->chip[chipnr]->int_cpu_reg = 0;
283 candev->chip[chipnr]->int_clk_reg = 0;
284 candev->chip[chipnr]->int_bus_reg = 0;
285 candev->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
286 candev->chip[chipnr]->sja_ocr_reg =
287 OCR_MODE_NORMAL | OCR_TX0_LH;
290 candev->chip[chipnr]->clock = 16000000;
295 int pccan_init_obj_data(struct chip_t *chip, int objnr)
297 if (!strcmp(chip->chip_type,"sja1000")) {
298 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
299 chip->msgobj[objnr]->flags=0;
301 else { /* The spacing for this card is 0x3c0 */
302 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
303 chip->msgobj[objnr]->flags=0;
309 int pccan_program_irq(struct candevice_t *candev)
315 unsigned char irq_reg_value=0;
318 for (i=0; i<4; i++) {
319 switch (candev->chip[i]->chip_irq) {
324 irq_reg_value |= (IRQ3<<(i*2));
328 irq_reg_value |= (IRQ5<<(i*2));
332 irq_reg_value |= (IRQ9<<(i*2));
336 CANMSG("Supplied interrupt is not supported by the hardware\n");
341 outb(irq_reg_value,0x6000+candev->io_addr);
342 DEBUGMSG("Configured pccan hardware interrupts\n");
343 outb(0x80,0x6000+candev->io_addr+0x02);
344 DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
349 inline void pccan_write_register(unsigned char data, unsigned long address)
354 unsigned pccan_read_register(unsigned long address)
359 int pccanf_register(struct hwspecops_t *hwspecops)
361 hwspecops->request_io = pccanf_request_io;
362 hwspecops->release_io = pccanf_release_io;
363 hwspecops->reset = pccanf_reset;
364 hwspecops->init_hw_data = pccan_init_hw_data;
365 hwspecops->init_chip_data = pccan_init_chip_data;
366 hwspecops->init_obj_data = pccan_init_obj_data;
367 hwspecops->write_register = pccan_write_register;
368 hwspecops->read_register = pccan_read_register;
369 hwspecops->program_irq = pccan_program_irq;
374 int pccand_register(struct hwspecops_t *hwspecops)
376 hwspecops->request_io = pccand_request_io;
377 hwspecops->release_io = pccand_release_io;
378 hwspecops->reset = pccand_reset;
379 hwspecops->init_hw_data = pccan_init_hw_data;
380 hwspecops->init_chip_data = pccan_init_chip_data;
381 hwspecops->init_obj_data = pccan_init_obj_data;
382 hwspecops->write_register = pccan_write_register;
383 hwspecops->read_register = pccan_read_register;
384 hwspecops->program_irq = pccan_program_irq;
389 int pccanq_register(struct hwspecops_t *hwspecops)
391 hwspecops->request_io = pccanq_request_io;
392 hwspecops->release_io = pccanq_release_io;
393 hwspecops->reset = pccanq_reset;
394 hwspecops->init_hw_data = pccan_init_hw_data;
395 hwspecops->init_chip_data = pccan_init_chip_data;
396 hwspecops->init_obj_data = pccan_init_obj_data;
397 hwspecops->write_register = pccan_write_register;
398 hwspecops->read_register = pccan_read_register;
399 hwspecops->program_irq = pccan_program_irq;