lincan/src/pccan.c

   1 /**************************************************************************/
   2 /* File: pccan.c - PCcan-Q/F/S/D ISA card by KVASER                       */
   3 /*                                                                        */
   4 /* LinCAN - (Not only) Linux CAN bus driver                               */
   5 /* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz>   */
   6 /* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>             */
   7 /* Funded by OCERA and FRESCOR IST projects                               */
   8 /* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl>      */
   9 /*                                                                        */
  10 /* LinCAN is free software; you can redistribute it and/or modify it      */
  11 /* under terms of the GNU General Public License as published by the      */
  12 /* Free Software Foundation; either version 2, or (at your option) any    */
  13 /* later version.  LinCAN is distributed in the hope that it will be      */
  14 /* useful, but WITHOUT ANY WARRANTY; without even the implied warranty    */
  15 /* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU    */
  16 /* General Public License for more details. You should have received a    */
  17 /* copy of the GNU General Public License along with LinCAN; see file     */
  18 /* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave,  */
  19 /* Cambridge, MA 02139, USA.                                              */
  20 /*                                                                        */
  21 /* To allow use of LinCAN in the compact embedded systems firmware        */
  22 /* and RT-executives (RTEMS for example), main authors agree with next    */
  23 /* special exception:                                                     */
  24 /*                                                                        */
  25 /* Including LinCAN header files in a file, instantiating LinCAN generics */
  26 /* or templates, or linking other files with LinCAN objects to produce    */
  27 /* an application image/executable, does not by itself cause the          */
  28 /* resulting application image/executable to be covered by                */
  29 /* the GNU General Public License.                                        */
  30 /* This exception does not however invalidate any other reasons           */
  31 /* why the executable file might be covered by the GNU Public License.    */
  32 /* Publication of enhanced or derived LinCAN files is required although.  */
  33 /**************************************************************************/
  34
  35 #include "../include/can.h"
  36 #include "../include/can_sysdep.h"
  37 #include "../include/main.h"
  38 #include "../include/pccan.h"
  39 #include "../include/i82527.h"
  40 #include "../include/sja1000.h"
  41
  42 int pccanf_request_io(struct candevice_t *candev)
  43 {
  44         if (!can_request_io_region(candev->io_addr+0x4000,0x20,DEVICE_NAME)) {
  45                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x4000);
  46                 return -ENODEV;
  47         }
  48         else if (!can_request_io_region(candev->io_addr+0x6000,0x04,DEVICE_NAME)) {
  49                 can_release_io_region(candev->io_addr+0x4000,0x20);
  50                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x6000);
  51                 return -ENODEV;
  52         }
  53         else {
  54                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x4000, candev->io_addr+0x4000+0x20-1);
  55                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x6000, candev->io_addr+0x6000+0x04-1);
  56         }
  57         return 0;
  58 }
  59
  60 int pccand_request_io(struct candevice_t *candev)
  61 {
  62         if (pccanf_request_io(candev))
  63                 return -ENODEV;
  64
  65         if (!can_request_io_region(candev->io_addr+0x5000,0x20,DEVICE_NAME)) {
  66                 pccanf_release_io(candev);
  67                 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x5000);
  68                 return -ENODEV;
  69         }
  70         else {
  71                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x5000, candev->io_addr+0x5000+0x20-1);
  72         }
  73         return 0;
  74 }
  75
  76 int pccanq_request_io(struct candevice_t *candev)
  77 {
  78         unsigned long io_addr;
  79         int i;
  80
  81         if (pccand_request_io(candev))
  82                 return -ENODEV;
  83
  84         for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
  85                 if (!can_request_io_region(io_addr,0x40,DEVICE_NAME)) {
  86                         CANMSG("Unable to open port: 0x%lx\n",io_addr);
  87                         while(i--){
  88                                 io_addr-=0x400;
  89                                 can_release_io_region(io_addr,0x40);
  90                         }
  91                         pccand_release_io(candev);
  92                         return -ENODEV;
  93                 }
  94                 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, io_addr+0x40-1);
  95         }
  96         return 0;
  97 }
  98
  99 int pccanf_release_io(struct candevice_t *candev)
 100 {
 101         can_release_io_region(candev->io_addr+0x4000,0x20);
 102         can_release_io_region(candev->io_addr+0x6000,0x04);
 103
 104         return 0;
 105 }
 106
 107 int pccand_release_io(struct candevice_t *candev)
 108 {
 109         pccanf_release_io(candev);
 110         can_release_io_region(candev->io_addr+0x5000,0x20);
 111
 112         return 0;
 113 }
 114
 115 int pccanq_release_io(struct candevice_t *candev)
 116 {
 117         unsigned long io_addr;
 118         int i;
 119
 120         pccand_release_io(candev);
 121
 122         for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
 123                 can_release_io_region(io_addr,0x40);
 124         }
 125
 126         return 0;
 127 }
 128
 129 int pccanf_reset(struct candevice_t *candev)
 130 {
 131         int i=0;
 132
 133         DEBUGMSG("Resetting pccanf/s hardware ...\n");
 134         while (i < 1000000) {
 135                 i++;
 136                 can_outb(0x00,candev->res_addr);
 137         }
 138         can_outb(0x01,candev->res_addr);
 139         can_outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
 140
 141         /* Check hardware reset status */
 142         i=0;
 143         while ( (can_inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
 144                                                                  && (i<=15) ) {
 145                 mdelay(20);
 146                 i++;
 147         }
 148         if (i>=15) {
 149                 CANMSG("Reset status timeout!\n");
 150                 CANMSG("Please check your hardware.\n");
 151                 return -ENODEV;
 152         }
 153         else
 154                 DEBUGMSG("Chip[0] reset status ok.\n");
 155
 156         return 0;
 157 }
 158
 159 int pccand_reset(struct candevice_t *candev)
 160 {
 161         int i=0,chip_nr=0;
 162
 163         DEBUGMSG("Resetting pccan-d hardware ...\n");
 164         while (i < 1000000) {
 165                 i++;
 166                 can_outb(0x00,candev->res_addr);
 167         }
 168         can_outb(0x01,candev->res_addr);
 169         can_outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
 170         can_outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
 171
 172         /* Check hardware reset status */
 173         i=0;
 174         for (chip_nr=0; chip_nr<2; chip_nr++) {
 175                 i=0;
 176                 while ( (can_inb(candev->chip[chip_nr]->chip_base_addr +
 177                                                 SJACR) & sjaCR_RR) && (i<=15) ) {
 178                         mdelay(20);
 179                         i++;
 180                 }
 181                 if (i>=15) {
 182                         CANMSG("Reset status timeout!\n");
 183                         CANMSG("Please check your hardware.\n");
 184                         return -ENODEV;
 185                 }
 186                 else
 187                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 188         }
 189         return 0;
 190 }
 191
 192 int pccanq_reset(struct candevice_t *candev)
 193 {
 194         int i=0,chip_nr=0;
 195
 196         for (i=0; i<4; i++)
 197                 can_disable_irq(candev->chip[i]->chip_irq);
 198
 199         DEBUGMSG("Resetting pccan-q hardware ...\n");
 200         while (i < 100000) {
 201                 i++;
 202                 can_outb(0x00,candev->res_addr);
 203         }
 204         outb_p(0x01,candev->res_addr);
 205
 206         can_outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
 207         can_outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
 208
 209         /* Check hardware reset status */
 210         for (chip_nr=0; chip_nr<2; chip_nr++) {
 211                 i=0;
 212                 while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
 213                                                 iCPU) & iCPU_RST) && (i<=15) ) {
 214                         mdelay(20);
 215                         i++;
 216                 }
 217                 if (i>=15) {
 218                         CANMSG("Reset status timeout!\n");
 219                         CANMSG("Please check your hardware.\n");
 220                         return -ENODEV;
 221                 }
 222                 else
 223                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 224         }
 225         for (chip_nr=2; chip_nr<4; chip_nr++) {
 226                 i=0;
 227                 while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
 228                                                 SJACR) & sjaCR_RR) && (i<=15) ) {
 229                         mdelay(20);
 230                         i++;
 231                 }
 232                 if (i>=15) {
 233                         CANMSG("Reset status timeout!\n");
 234                         CANMSG("Please check your hardware.\n");
 235                         return -ENODEV;
 236                 }
 237                 else
 238                         DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
 239         }
 240
 241         for (i=0; i<4; i++)
 242                 can_enable_irq(candev->chip[i]->chip_irq);
 243
 244         return 0;
 245 }
 246
 247 int pccan_init_hw_data(struct candevice_t *candev)
 248 {
 249         candev->res_addr=candev->io_addr+0x6001;
 250         candev->flags |= CANDEV_PROGRAMMABLE_IRQ;
 251
 252         if (!strcmp(candev->hwname,"pccan-q")) {
 253                 candev->nr_82527_chips=2;
 254                 candev->nr_sja1000_chips=2;
 255                 candev->nr_all_chips=4;
 256         }
 257         if (!strcmp(candev->hwname,"pccan-f") |
 258             !strcmp(candev->hwname,"pccan-s")) {
 259                 candev->nr_82527_chips=0;
 260                 candev->nr_sja1000_chips=1;
 261                 candev->nr_all_chips=1;
 262         }
 263         if (!strcmp(candev->hwname,"pccan-d")) {
 264                 candev->nr_82527_chips=0;
 265                 candev->nr_sja1000_chips=2;
 266                 candev->nr_all_chips=2;
 267         }
 268
 269         return 0;
 270 }
 271
 272 int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
 273 {
 274         if (!strcmp(candev->hwname,"pccan-q")) {
 275                 if (chipnr<2) {
 276                         i82527_fill_chipspecops(candev->chip[chipnr]);
 277                         candev->chip[chipnr]->flags = CHIP_SEGMENTED;
 278                         candev->chip[chipnr]->int_cpu_reg=iCPU_DSC;
 279                         candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
 280                         candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
 281                         candev->chip[chipnr]->sja_cdr_reg = 0;
 282                         candev->chip[chipnr]->sja_ocr_reg = 0;
 283                 }
 284                 else{
 285                         sja1000_fill_chipspecops(candev->chip[chipnr]);
 286                         candev->chip[chipnr]->flags = 0;
 287                         candev->chip[chipnr]->int_cpu_reg = 0;
 288                         candev->chip[chipnr]->int_clk_reg = 0;
 289                         candev->chip[chipnr]->int_bus_reg = 0;
 290                         candev->chip[chipnr]->sja_cdr_reg =
 291                                                                 sjaCDR_CLK_OFF;
 292                         candev->chip[chipnr]->sja_ocr_reg =
 293                                                 sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
 294                 }
 295                 candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(0x1000*chipnr+0x2000+candev->io_addr);
 296         }
 297         else {
 298                 sja1000_fill_chipspecops(candev->chip[chipnr]);
 299                 candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(0x1000*chipnr+0x4000+candev->io_addr);
 300                 candev->chip[chipnr]->flags = 0;
 301                 candev->chip[chipnr]->int_cpu_reg = 0;
 302                 candev->chip[chipnr]->int_clk_reg = 0;
 303                 candev->chip[chipnr]->int_bus_reg = 0;
 304                 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
 305                 candev->chip[chipnr]->sja_ocr_reg =
 306                                                 sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
 307         }
 308
 309         candev->chip[chipnr]->clock = 16000000;
 310
 311         return 0;
 312 }
 313
 314 int pccan_init_obj_data(struct canchip_t *chip, int objnr)
 315 {
 316         if (!strcmp(chip->chip_type,"sja1000")) {
 317                 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
 318                 }
 319         else {  /* The spacing for this card is 0x3c0 */
 320                 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
 321                 }
 322
 323         return 0;
 324 }
 325
 326 int pccan_program_irq(struct candevice_t *candev)
 327 {
 328         #define IRQ9 0x01
 329         #define IRQ3 0x02
 330         #define IRQ5 0x03
 331
 332         unsigned char irq_reg_value=0;
 333         int i;
 334
 335         for (i=0; i<4; i++) {
 336                 switch (candev->chip[i]->chip_irq) {
 337                         case 0: {
 338                                 break;
 339                         }
 340                         case 3: {
 341                                 irq_reg_value |= (IRQ3<<(i*2));
 342                                 break;
 343                         }
 344                         case 5: {
 345                                 irq_reg_value |= (IRQ5<<(i*2));
 346                                 break;
 347                         }
 348                         case 9: {
 349                                 irq_reg_value |= (IRQ9<<(i*2));
 350                                 break;
 351                         }
 352                         default: {
 353                                 CANMSG("Supplied interrupt is not supported by the hardware\n");
 354                                 return -ENODEV;
 355                         }
 356                 }
 357         }
 358         can_outb(irq_reg_value,0x6000+candev->io_addr);
 359         DEBUGMSG("Configured pccan hardware interrupts\n");
 360         can_outb(0x80,0x6000+candev->io_addr+0x02);
 361         DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
 362
 363         return 0;
 364 }
 365
 366 inline void pccan_write_register(unsigned data, can_ioptr_t address)
 367 {
 368         can_outb(data,address);
 369 }
 370
 371 unsigned pccan_read_register(can_ioptr_t address)
 372 {
 373         return can_inb(address);
 374 }
 375
 376 int pccanf_register(struct hwspecops_t *hwspecops)
 377 {
 378         hwspecops->request_io = pccanf_request_io;
 379         hwspecops->release_io = pccanf_release_io;
 380         hwspecops->reset = pccanf_reset;
 381         hwspecops->init_hw_data = pccan_init_hw_data;
 382         hwspecops->init_chip_data = pccan_init_chip_data;
 383         hwspecops->init_obj_data = pccan_init_obj_data;
 384         hwspecops->write_register = pccan_write_register;
 385         hwspecops->read_register = pccan_read_register;
 386         hwspecops->program_irq = pccan_program_irq;
 387         return 0;
 388 }
 389
 390
 391 int pccand_register(struct hwspecops_t *hwspecops)
 392 {
 393         hwspecops->request_io = pccand_request_io;
 394         hwspecops->release_io = pccand_release_io;
 395         hwspecops->reset = pccand_reset;
 396         hwspecops->init_hw_data = pccan_init_hw_data;
 397         hwspecops->init_chip_data = pccan_init_chip_data;
 398         hwspecops->init_obj_data = pccan_init_obj_data;
 399         hwspecops->write_register = pccan_write_register;
 400         hwspecops->read_register = pccan_read_register;
 401         hwspecops->program_irq = pccan_program_irq;
 402         return 0;
 403 }
 404
 405
 406 int pccanq_register(struct hwspecops_t *hwspecops)
 407 {
 408         hwspecops->request_io = pccanq_request_io;
 409         hwspecops->release_io = pccanq_release_io;
 410         hwspecops->reset = pccanq_reset;
 411         hwspecops->init_hw_data = pccan_init_hw_data;
 412         hwspecops->init_chip_data = pccan_init_chip_data;
 413         hwspecops->init_obj_data = pccan_init_obj_data;
 414         hwspecops->write_register = pccan_write_register;
 415         hwspecops->read_register = pccan_read_register;
 416         hwspecops->program_irq = pccan_program_irq;
 417         return 0;
 418 }