2 * Header file for the Linux CAN-bus driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.3 17 Jun 2004
10 int sja1000_enable_configuration(struct canchip_t *chip);
11 int sja1000_disable_configuration(struct canchip_t *chip);
12 int sja1000_chip_config(struct canchip_t *chip);
13 int sja1000_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask);
14 int sja1000_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
15 int sampl_pt, int flags);
16 int sja1000_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
17 int sja1000_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
18 struct canmsg_t *msg);
19 int sja1000_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
20 struct canmsg_t *msg);
21 int sja1000_check_tx_stat(struct canchip_t *chip);
22 int sja1000_set_btregs(struct canchip_t *chip, unsigned short btr0,
24 int sja1000_start_chip(struct canchip_t *chip);
25 int sja1000_stop_chip(struct canchip_t *chip);
26 int sja1000_irq_handler(int irq, struct canchip_t *chip);
27 int sja1000_fill_chipspecops(struct canchip_t *chip);
29 /* BasicCAN mode address map */
30 #define SJACR 0x00 /* Control register */
31 #define SJACMR 0x01 /* Command register */
32 #define SJASR 0x02 /* Status register */
33 #define SJAIR 0x03 /* Interrupt register */
34 #define SJAACR 0x04 /* Acceptance Code register */
35 #define SJAAMR 0x05 /* Acceptance Mask Register */
36 #define SJABTR0 0x06 /* Bus Timing register 0 */
37 #define SJABTR1 0x07 /* Bus Timing register 1 */
38 #define SJAOCR 0x08 /* Output Control register */
39 #define SJACDR 0x1f /* Clock Divider register */
41 #define SJATXID1 0x0a /* Identifier byte 1 */
42 #define SJATXID0 0x0b /* Identifier byte 0 */
43 #define SJATXDAT0 0x0c /* First data byte */
44 #define SJATXDAT1 0x0d
45 #define SJATXDAT2 0x0e
46 #define SJATDDAT3 0x0f
47 #define SJATXDAT4 0x10
48 #define SJATXDAT5 0x11
49 #define SJATXDAT6 0x12
50 #define SJATXDAT7 0x13
52 #define SJARXID1 0x14 /* Identifier byte 1 */
53 #define SJARXID0 0x15 /* Identifier byte 0 */
54 #define SJARXDAT0 0x16 /* First data byte */
55 #define SJARXDAT1 0x17
56 #define SJARXDAT2 0x18
57 #define SJARXDAT3 0x19
58 #define SJARXDAT4 0x1a
59 #define SJARXDAT5 0x1b
60 #define SJARXDAT6 0x1c
61 #define SJARXDAT7 0x1d
63 /* Command register */
64 enum sja1000_BASIC_CMR {
65 sjaCMR_TR = 1, // Transmission request
66 sjaCMR_AT = 1<<1, // Abort Transmission
67 sjaCMR_RRB = 1<<2, // Release Receive Buffer
68 sjaCMR_CDO = 1<<3, // Clear Data Overrun
69 sjaCMR_GTS = 1<<4 // Go To Sleep
73 enum sja1000_BASIC_SR {
74 sjaSR_RBS = 1, // Receive Buffer Status
75 sjaSR_DOS = 1<<1, // Data Overrun Status
76 sjaSR_TBS = 1<<2, // Transmit Buffer Status
77 sjaSR_TCS = 1<<3, // Transmission Complete Status
78 sjaSR_RS = 1<<4, // Receive Status
79 sjaSR_TS = 1<<5, // Transmit Status
80 sjaSR_ES = 1<<6, // Error Status
81 sjaSR_BS = 1<<7 // Bus Status
84 /* Control Register */
85 enum sja1000_BASIC_CR {
86 sjaCR_RR = 1, // Reset Request
87 sjaCR_RIE = 1<<1, // Receive Interrupt Enable
88 sjaCR_TIE = 1<<2, // Transmit Interrupt Enable
89 sjaCR_EIE = 1<<3, // Error Interrupt Enable
90 sjaCR_OIE = 1<<4 // Overrun Interrupt Enable
93 /* Interrupt (status) Register */
94 enum sja1000_BASIC_IR {
95 sjaIR_RI = 1, // Receive Interrupt
96 sjaIR_TI = 1<<1, // Transmit Interrupt
97 sjaIR_EI = 1<<2, // Error Interrupt
98 sjaIR_DOI = 1<<3, // Data Overrun Interrupt
99 sjaIR_WUI = 1<<4 // Wake-Up Interrupt
102 /* Clock Divider Register */
104 /* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
105 sjaCDR_CLKOUT_DIV1 = 7,
106 sjaCDR_CLKOUT_DIV2 = 0,
107 sjaCDR_CLKOUT_DIV4 = 1,
108 sjaCDR_CLKOUT_DIV6 = 2,
109 sjaCDR_CLKOUT_DIV8 = 3,
110 sjaCDR_CLKOUT_DIV10 = 4,
111 sjaCDR_CLKOUT_DIV12 = 5,
112 sjaCDR_CLKOUT_DIV14 = 6,
113 sjaCDR_CLKOUT_MASK = 7,
114 sjaCDR_CLK_OFF = 1<<3, // Clock Off
115 sjaCDR_RXINPEN = 1<<5, // TX1 output is RX irq output
116 sjaCDR_CBP = 1<<6, // Input Comparator By-Pass
117 sjaCDR_PELICAN = 1<<7 // PeliCAN Mode
120 /* Output Control Register */
122 sjaOCR_MODE_BIPHASE = 0,
123 sjaOCR_MODE_TEST = 1,
124 sjaOCR_MODE_NORMAL = 2,
125 sjaOCR_MODE_CLOCK = 3,
126 // TX0 push-pull not inverted
127 sjaOCR_TX0_LH = 0x18,
128 // TX0 push-pull inverted
129 sjaOCR_TX0_HL = 0x1c,
130 // TX1 floating (off)
132 // TX1 pull-down not inverted
136 /** Frame format information 0x11 */
137 enum sja1000_BASIC_ID0 {
138 sjaID0_RTR = 1<<4, // Remote request
139 sjaID0_DLC_M = (1<<4)-1 // Length Mask