1 /* c_can.c - Hynix HMS30c7202 ARM generic C_CAN module handling
2 * Linux CAN-bus device driver.
3 * Written by Sebastian Stolzenberg email:stolzi@sebastian-stolzenberg.de
4 * Based on code from Arnaud Westenberg email:arnaud@wanadoo.nl
5 * and Ake Hedman, eurosource, akhe@eurosource.se
6 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
7 * email:pisa@cmp.felk.cvut.cz
8 * This software is released under the GPL-License.
9 * Version lincan-0.3 17 Jun 2004
12 #define __NO_VERSION__
14 #include "../include/can.h"
15 #include "../include/can_sysdep.h"
16 #include "../include/main.h"
17 #include "../include/c_can.h"
22 CAN_DEFINE_SPINLOCK(c_can_spwlock); // Spin lock for write operations
23 CAN_DEFINE_SPINLOCK(c_can_sprlock); // Spin lock for read operations
24 CAN_DEFINE_SPINLOCK(c_can_if1lock); // spin lock for the if1 register
25 CAN_DEFINE_SPINLOCK(c_can_if2lock); // spin lcok for the if2 register
28 * c_can_enable_configuration - enable chip configuration mode
29 * @pchip: pointer to chip state structure
31 int c_can_enable_configuration(struct canchip_t *pchip)
35 DEBUGMSG("(c%d)calling c_can_enable_configuration(...)\n",
38 DEBUGMSG("Trying disable_irq(...) : ");
40 disable_irq(chip->chip_irq);
42 //read Control Register
43 flags = c_can_read_reg_w(pchip, CCCR);
44 //set Init-Bit in the Control Register (10 tries)
45 while ((!(flags & CR_INIT)) && (i <= 10)) {
46 c_can_write_reg_w(pchip, flags | CR_INIT, CCCR);
49 flags = c_can_read_reg_w(pchip, CCCR);
52 CANMSG("Reset error\n");
53 //enable_irq(chip->chip_irq);
61 ///////////////////////////////////////////////////////////////////////
62 int c_can_disable_configuration(struct canchip_t *pchip)
67 DEBUGMSG("(c%d)calling c_can_disable_configuration(...)\n",
69 //read Control Register
70 flags = c_can_read_reg_w(pchip, CCCR);
72 //reset Init-Bit in the Control Register (10 tries)
73 while ((flags & CR_INIT) && (i <= 10)) {
74 c_can_write_reg_w(pchip, flags & ~CR_INIT, CCCR);
75 udelay(1000); //100 microseconds
77 flags = c_can_read_reg_w(pchip, CCCR);
80 CANMSG("Error leaving reset status\n");
84 //enable_irq(chip->chip_irq);
89 ///////////////////////////////////////////////////////////////////////
90 int c_can_chip_config(struct canchip_t *pchip)
93 DEBUGMSG("(c%d)calling c_can_chip_config(...)\n", pchip->chip_idx);
98 if (pchip->baudrate == 0)
99 pchip->baudrate = 1000000;
102 (pchip, pchip->baudrate, pchip->clock, 0, 75, 0)) {
103 CANMSG("Error configuring baud rate\n");
107 if (c_can_extended_mask(pchip,0x0000000,extmask)) {
108 CANMSG("Error configuring extended mask\n");
112 if (c_can_standard_mask(pchip,0x0000,stdmask)) {
113 CANMSG("Error configuring standard mask\n");
117 if (c_can_clear_objects(pchip)) {
118 CANMSG("Error clearing message objects\n");
121 if (c_can_config_irqs(pchip, CR_MIE | CR_SIE | CR_EIE)) {
122 CANMSG("Error configuring interrupts\n");
126 DEBUGMSG("-> Configured successfully\n");
129 c_can_registerdump(pchip);
135 ///////////////////////////////////////////////////////////////////////
137 * Checks if the Busy-Bit in the IF1-Command-Request Register is set
139 int c_can_if1_busycheck(struct canchip_t *pchip)
143 unsigned short comreg = 0;
145 comreg = c_can_read_reg_w(pchip, CCIF1CR);
146 while ((comreg & IFXCR_BUSY) && (i <= 100)) {
147 udelay(1); //1 microseconds
149 comreg = c_can_read_reg_w(pchip, CCIF1CR);
152 CANMSG("Error Busy-Bit stays set\n");
159 ///////////////////////////////////////////////////////////////////////
161 * Checks if the Busy-Bit in the IF2-Command-Request Register is set
163 int c_can_if2_busycheck(struct canchip_t *pchip)
167 unsigned short comreg = 0;
169 comreg = c_can_read_reg_w(pchip, CCIF2CR);
170 while ((comreg & IFXCR_BUSY) && (i <= 100)) {
171 udelay(1); //1 microseconds
173 comreg = c_can_read_reg_w(pchip, CCIF2CR);
176 CANMSG("Error Busy-Bit stays set\n");
183 ///////////////////////////////////////////////////////////////////////
185 * Though the C-CAN Chip can handle one mask for each Message Object, this Method defines
186 * one mask for all MOs. That means every MO gets the same mask.
189 /* Set communication parameters.
190 * param rate baud rate in Hz
191 * param clock frequency of C-CAN clock in Hz
192 * param sjw synchronization jump width (0-3) prescaled clock cycles
193 * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
194 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
196 int c_can_baud_rate(struct canchip_t *pchip, int rate, int clock,
197 int sjw, int sampl_pt, int flags)
199 int best_error = 1000000000, error;
200 int best_tseg = 0, best_brp = 0, best_rate = 0, brp = 0;
201 int tseg = 0, tseg1 = 0, tseg2 = 0;
203 unsigned short tempCR = 0;
205 DEBUGMSG("(c%d)calling c_can_baud_rate(...)\n", pchip->chip_idx);
207 if (c_can_enable_configuration(pchip))
210 /* tseg even = round down, odd = round up */
211 for (tseg = (0 + 0 + 2) * 2;
212 tseg <= (MAX_TSEG2 + MAX_TSEG1 + 2) * 2 + 1; tseg++) {
213 brp = clock / ((1 + tseg / 2) * rate) + tseg % 2;
214 if (brp == 0 || brp > 64)
216 error = rate - clock / (brp * (1 + tseg / 2));
219 if (error <= best_error) {
221 best_tseg = tseg / 2;
223 best_rate = clock / (brp * (1 + tseg / 2));
226 if (best_error && (rate / best_error < 10)) {
227 CANMSG("baud rate %d is not possible with %d Hz clock\n",
229 CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
230 best_rate, best_brp, best_tseg, tseg1, tseg2);
233 tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100;
236 if (tseg2 > MAX_TSEG2)
238 tseg1 = best_tseg - tseg2 - 2;
239 if (tseg1 > MAX_TSEG1) {
241 tseg2 = best_tseg - tseg1 - 2;
244 DEBUGMSG("-> Setting %d bps.\n", best_rate);
245 DEBUGMSG("->brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
246 best_brp, best_tseg, tseg1, tseg2,
247 (100 * (best_tseg - tseg2) / (best_tseg + 1)));
249 //read Control Register
250 tempCR = c_can_read_reg_w(pchip, CCCR);
251 //Configuration Change Enable
252 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
253 c_can_write_reg_w(pchip,
254 ((unsigned short)tseg2) << 12 | ((unsigned short)
256 (unsigned short)sjw << 6 | (unsigned short)best_brp,
259 if (c_can_disable_configuration(pchip))
265 ///////////////////////////////////////////////////////////////////////
266 int c_can_mask(struct msgobj_t *pmsgobj, u32 mask, u16 usedirbit)
268 unsigned short tempreg = 0;
269 unsigned short readMaskCM;
270 unsigned short writeMaskCM;
272 DEBUGMSG("(c%dm%d)calling c_can_mask(...)\n",
273 pmsgobj->hostchip->chip_idx, pmsgobj->object);
275 readMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK;
276 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_MASK | IFXCM_WRRD;
278 spin_lock(&c_can_if1lock);
280 //load Message Object in IF1
281 if (c_can_if1_busycheck(pmsgobj->hostchip))
283 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
284 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
286 //setting Message Valid Bit to zero
287 if (c_can_if1_busycheck(pmsgobj->hostchip))
289 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
290 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~(IFXARB2_MVAL),
292 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
293 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
295 //setting UMask, MsgVal and Mask Register
296 if (c_can_if1_busycheck(pmsgobj->hostchip))
299 //set indication, that mask is used
300 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
301 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
304 //writing acceptance mask for extended or standart mode
305 if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
307 c_can_write_reg_w(pmsgobj->hostchip,
308 (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD |
309 IFXMSK2_MDIR, CCIF1M2);
311 c_can_write_reg_w(pmsgobj->hostchip,
312 (mask >> 16 & 0x1FFF) | IFXMSK2_MXTD,
314 c_can_write_reg_w(pmsgobj->hostchip, (mask & 0xFFFF), CCIF1M1);
317 c_can_write_reg_w(pmsgobj->hostchip,
318 ((mask << 2) & 0x1FFC) | IFXMSK2_MDIR,
321 c_can_write_reg_w(pmsgobj->hostchip,
322 ((mask << 2) & 0x1FFC), CCIF1M2);
323 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1M1);
326 //seting Message Valid Bit to one
327 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
328 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
330 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
331 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
333 spin_unlock(&c_can_if1lock);
335 DEBUGMSG("-> Setting acceptance mask to 0x%lx\n", (unsigned long)mask);
338 c_can_registerdump(pmsgobj->hostchip);
344 ///////////////////////////////////////////////////////////////////////
345 int c_can_use_mask(struct msgobj_t *pmsgobj, u16 useflag)
347 unsigned short tempreg = 0;
348 unsigned short readMaskCM;
349 unsigned short writeMaskCM;
352 char *boolstring = "false";
356 DEBUGMSG("(c%dm%d)calling c_can_use_mask(...)\n",
357 pmsgobj->hostchip->chip_idx, pmsgobj->object);
359 readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
360 writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;;
362 spin_lock(&c_can_if1lock);
364 //load Message Object in IF1
365 if (c_can_if1_busycheck(pmsgobj->hostchip))
367 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
368 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
370 //setting Message Valid Bit to zero
371 if (c_can_if1_busycheck(pmsgobj->hostchip))
373 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
374 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
375 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
376 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
379 if (c_can_if1_busycheck(pmsgobj->hostchip))
382 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
383 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXMC_UMASK,
386 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
387 c_can_write_reg_w(pmsgobj->hostchip, tempreg & ~IFXMC_UMASK,
390 //seting Message Valid Bit to one
391 tempreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1A2);
392 c_can_write_reg_w(pmsgobj->hostchip, tempreg | IFXARB2_MVAL, CCIF1A2);
394 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
395 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
397 spin_unlock(&c_can_if1lock);
400 DEBUGMSG("-> Setting umask bit to %s\n", boolstring);
403 c_can_registerdump(pmsgobj->hostchip);
409 ///////////////////////////////////////////////////////////////////////
410 int c_can_clear_objects(struct canchip_t *pchip)
412 unsigned short i = 0;
413 unsigned short tempreg = 0;
415 unsigned short maskCM = IFXCM_ARB;
417 DEBUGMSG("(c%d)calling c_can_clear_objects(...)\n", pchip->chip_idx);
419 spin_lock(&c_can_if1lock);
420 spin_lock(&c_can_if2lock);
422 for (i = 0; i < 0x10; i++) {
424 //loading Message Objects in IF1 and IF2
425 if (c_can_if1_busycheck(pchip))
427 c_can_write_reg_w(pchip, maskCM, CCIF1CM);
428 c_can_write_reg_w(pchip, i, CCIF1CR);
429 if (c_can_if2_busycheck(pchip))
431 c_can_write_reg_w(pchip, maskCM, CCIF2CM);
432 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
434 //setting Message Valid Bit to zero
435 if (c_can_if1_busycheck(pchip))
437 tempreg = c_can_read_reg_w(pchip, CCIF1A2);
438 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF1A2);
439 c_can_write_reg_w(pchip, i, CCIF1CR);
440 if (c_can_if2_busycheck(pchip))
442 tempreg = c_can_read_reg_w(pchip, CCIF2A2);
443 c_can_write_reg_w(pchip, tempreg & ~IFXARB2_MVAL, CCIF2A2);
444 c_can_write_reg_w(pchip, i + 0x10, CCIF2CR);
447 for (i = 0; i < pchip->max_objects; i++) {
448 if (can_msgobj_test_fl(pchip->msgobj[i], OPENED)) {
449 // In- and output buffer re-initialization
450 canqueue_ends_flush_inlist(pchip->msgobj[i]->qends);
451 canqueue_ends_flush_outlist(pchip->msgobj[i]->qends);
456 spin_unlock(&c_can_if1lock);
457 spin_unlock(&c_can_if2lock);
459 DEBUGMSG("-> Message Objects reset\n");
464 ///////////////////////////////////////////////////////////////////////
465 int c_can_config_irqs(struct canchip_t *pchip, u16 irqs)
469 DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
471 tempreg = c_can_read_reg_w(pchip, CCCR);
472 DEBUGMSG("-> CAN Control Register: 0x%4lx\n", (long)tempreg);
473 c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
474 DEBUGMSG("-> Configured hardware interrupt delivery\n");
478 ///////////////////////////////////////////////////////////////////////
479 int c_can_pre_read_config(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
481 unsigned short readMaskCM = IFXCM_CNTRL | IFXCM_ARB;
482 unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
483 unsigned short mcreg = 0;
484 u32 id = pmsgobj->rx_preconfig_id;
486 DEBUGMSG("(c%dm%d)calling c_can_pre_read_config(...)\n",
487 pmsgobj->hostchip->chip_idx, pmsgobj->object);
489 spin_lock(&c_can_if1lock);
491 if (c_can_if1_busycheck(pmsgobj->hostchip))
494 //loading Message Object in IF1
495 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
496 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
498 if (c_can_if1_busycheck(pmsgobj->hostchip))
501 //setting Message Valid Bit to zero
502 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
503 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
504 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
506 /* Only access when the C_CAN controller is idle */
507 if (c_can_if1_busycheck(pmsgobj->hostchip))
510 //Configuring Message-Object
511 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
512 c_can_write_reg_w(pmsgobj->hostchip,
513 ((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE),
516 //writing arbitration mask for extended or standart mode
517 if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
518 c_can_write_reg_w(pmsgobj->hostchip,
519 IFXARB2_XTD | IFXARB2_MVAL | (id >> 16 &
522 c_can_write_reg_w(pmsgobj->hostchip, id & 0xFFFF, CCIF1A1);
524 c_can_write_reg_w(pmsgobj->hostchip,
525 IFXARB2_MVAL | (id << 2 & 0x1FFC), CCIF1A2);
526 //c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
528 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
529 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
531 spin_unlock(&c_can_if1lock);
533 DEBUGMSG("-> Receiving through message object %d with id=%d\n",
534 pmsgobj->object, id);
536 c_can_registerdump(pmsgobj->hostchip);
542 CANMSG("Timeout in c_can_if1_busycheck\n");
543 spin_unlock(&c_can_if1lock);
548 ///////////////////////////////////////////////////////////////////////
549 int c_can_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
550 struct canmsg_t *msg)
555 ///////////////////////////////////////////////////////////////////////
557 *Prepare the Chip to send specified Message over specified Messageobject
558 *In this version the method also sends the message.
561 int c_can_send_msg(struct canchip_t *pchip, struct msgobj_t *pmsgobj,
562 struct canmsg_t *pmsg)
564 unsigned short readMaskCM =
565 IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB;
566 unsigned short writeMaskCM =
567 IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD;
568 unsigned short writeSendMskCM =
569 IFXCM_CNTRL | IFXCM_ARB | IFXCM_DA | IFXCM_DB | IFXCM_WRRD |
571 unsigned short mcreg = 0;
572 //unsigned short arbreg = 0;
573 unsigned short dataA1 = 0;
574 unsigned short dataA2 = 0;
575 unsigned short dataB1 = 0;
576 unsigned short dataB2 = 0;
578 DEBUGMSG("(c%dm%d)calling c_can_send_msg(...)\n",
579 pmsgobj->hostchip->chip_idx, pmsgobj->object);
581 spin_lock(&c_can_if2lock);
583 can_msgobj_clear_fl(pmsgobj, RX_MODE);
585 //loading Message Object in IF1
586 if (c_can_if2_busycheck(pmsgobj->hostchip))
588 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF2CM);
589 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
590 //setting Message Valid Bit to zero
591 if (c_can_if2_busycheck(pmsgobj->hostchip))
593 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF2A2);
594 c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF2CM);
595 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
597 if (c_can_if2_busycheck(pmsgobj->hostchip))
599 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF2CM);
601 //define Command Mask
602 c_can_write_reg_w(pmsgobj->hostchip,
603 (mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_TXIE |
604 IFXMC_RMTEN | IFXMC_NEWDAT | IFXMC_TXRQST | (pmsg->
608 //set Arbitration Bits
609 if (can_msgobj_test_fl(pmsgobj, RX_MODE_EXT)) {
610 c_can_write_reg_w(pmsgobj->hostchip, (u16) (pmsg->id), CCIF2A1);
611 c_can_write_reg_w(pmsgobj->hostchip,
612 IFXARB2_XTD | IFXARB2_MVAL | IFXARB2_DIR |
613 ((u16) (pmsg->id >> 16) & 0x1FFF), CCIF2A2);
615 c_can_write_reg_w(pmsgobj->hostchip,
616 (IFXARB2_MVAL | IFXARB2_DIR |
617 ((u16) (pmsg->id << 2) & 0x1FFC)), CCIF2A2);
618 c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A1);
621 if (pmsg->length > 0) {
622 dataA1 = pmsg->data[0] | (u16) pmsg->data[1] << 8;
623 dataA2 = pmsg->data[2] | (u16) pmsg->data[3] << 8;
624 dataB1 = pmsg->data[4] | (u16) pmsg->data[5] << 8;
625 dataB2 = pmsg->data[6] | (u16) pmsg->data[7] << 8;
627 c_can_write_reg_w(pmsgobj->hostchip, dataA1, CCIF2DA1);
628 c_can_write_reg_w(pmsgobj->hostchip, dataA2, CCIF2DA2);
629 c_can_write_reg_w(pmsgobj->hostchip, dataB1, CCIF2DB1);
630 c_can_write_reg_w(pmsgobj->hostchip, dataB2, CCIF2DB2);
633 c_can_write_reg_w(pmsgobj->hostchip, writeSendMskCM, CCIF2CM);
634 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF2CR);
636 spin_unlock(&c_can_if2lock);
640 c_can_registerdump(pmsgobj->hostchip);
646 //////////////////////////////////////////////////////////////////////
647 int c_can_remote_request(struct canchip_t *pchip, struct msgobj_t *pmsgobj)
649 unsigned short readMaskCM = IFXCM_CNTRL; // | IFXCM_ARB;
650 //unsigned short writeMaskCM = IFXCM_CNTRL | IFXCM_ARB | IFXCM_WRRD;
651 unsigned short mcreg = 0;
653 DEBUGMSG("(c%dm%d)calling c_can_remote_request(...)\n",
654 pmsgobj->hostchip->chip_idx, pmsgobj->object);
656 //Remote request is only available when the message object is in receiving mode
657 if (!can_msgobj_test_fl(pmsgobj, RX_MODE)) {
661 spin_lock(&c_can_if1lock);
663 //loading Message Object in IF1
664 if (c_can_if1_busycheck(pmsgobj->hostchip))
666 c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
667 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
668 //setting Transmit-Request-Bit
669 if (c_can_if1_busycheck(pmsgobj->hostchip))
671 mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1DMC);
672 c_can_write_reg_w(pmsgobj->hostchip, mcreg | IFXMC_TXRQST, CCIF1DMC);
674 c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
676 spin_unlock(&c_can_if1lock);
678 DEBUGMSG("-> Sent remote request through message object %d\n",
681 c_can_registerdump(pmsgobj->hostchip);
687 ///////////////////////////////////////////////////////////////////////
688 int c_can_set_btregs(struct canchip_t *pchip, u16 btr0, u16 btr1)
690 unsigned short tempCR = 0;
692 DEBUGMSG("(c%d)calling c_can_set_btregs(...)\n", pchip->chip_idx);
698 if (c_can_enable_configuration(pchip))
701 //read Control Register
702 tempCR = c_can_read_reg_w(pchip, CCCR);
703 //Configuration Change Enable
704 c_can_write_reg_w(pchip, tempCR | CR_CCE, CCCR);
705 c_can_write_reg_w(pchip, btr0 | (btr1 << 8), CCBT);
707 if (c_can_disable_configuration(pchip))
714 ///////////////////////////////////////////////////////////////////////
716 * Starts the Chip, by setting the CAN Enable Bit
718 int c_can_start_chip(struct canchip_t *pchip)
722 DEBUGMSG("(c%d)calling c_can_start_chip(...)\n", pchip->chip_idx);
726 DEBUGMSG("-> Error Chip not available.\n");
729 #ifdef C_CAN_WITH_CCCE
730 flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
731 c_can_write_reg_w(pchip, flags, CCCE);
736 c_can_registerdump(pchip);
742 ///////////////////////////////////////////////////////////////////////
744 * Stops the Chip, by deleting the CAN Enable Bit
746 int c_can_stop_chip(struct canchip_t *pchip)
750 DEBUGMSG("(c%d)calling c_can_stop_chip(...)\n", pchip->chip_idx);
754 DEBUGMSG("-> Error Chip not available.\n");
757 #ifdef C_CAN_WITH_CCCE
758 flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
759 c_can_write_reg_w(pchip, flags, CCCE);
766 int c_can_attach_to_chip(struct canchip_t *chip)
771 int c_can_release_chip(struct canchip_t *chip)
775 temp = c_can_read_reg_w(chip, CCCR);
777 /* Disable IRQ generation */
778 c_can_config_irqs(chip, 0);
780 temp = c_can_read_reg_w(chip, CCCR);
782 /* Power-down C_CAN, except this does nothing in the version 1.2 */
783 c_can_stop_chip(chip);
788 ///////////////////////////////////////////////////////////////////////
790 *Check the TxOK bit of the Status Register and resets it afterwards.
792 int c_can_check_tx_stat(struct canchip_t *pchip)
794 unsigned long tempstat = 0;
796 DEBUGMSG("(c%d)calling c_can_check_tx_stat(...)\n", pchip->chip_idx);
802 tempstat = c_can_read_reg_w(pchip, CCSR);
804 if (tempstat & SR_TXOK) {
805 c_can_write_reg_w(pchip, tempstat & ~SR_TXOK, CCSR);
812 ///////////////////////////////////////////////////////////////////////
813 int c_can_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
815 can_preempt_disable();
817 can_msgobj_set_fl(obj, TX_REQUEST);
819 /* calls c_can_irq_write_handler synchronized with other invocations
820 from kernel and IRQ context */
821 c_can_irq_sync_activities(chip, obj);
823 can_preempt_enable();
827 ///////////////////////////////////////////////////////////////////////
828 int c_can_filtch_rq(struct canchip_t *chip, struct msgobj_t *obj)
830 can_preempt_disable();
832 can_msgobj_set_fl(obj, FILTCH_REQUEST);
834 /* setups filter synchronized with other invocations from kernel and IRQ context */
835 c_can_irq_sync_activities(chip, obj);
837 can_preempt_enable();
841 ///////////////////////////////////////////////////////////////////////
842 void c_can_registerdump(struct canchip_t *pchip)
844 CANMSG("------------------------------------\n");
845 CANMSG("---------C-CAN Register Dump--------\n");
846 CANMSG("------------at 0x%.8lx-----------\n",
847 (unsigned long)pchip->chip_base_addr);
848 CANMSG("Control Register: 0x%.4lx\n",
849 (long)(c_can_read_reg_w(pchip, CCCR)));
850 CANMSG("Status Register: 0x%.4lx\n",
851 (long)(c_can_read_reg_w(pchip, CCSR)));
852 CANMSG("Error Counting Register: 0x%.4lx\n",
853 (long)(c_can_read_reg_w(pchip, CCEC)));
854 CANMSG("Bit Timing Register: 0x%.4lx\n",
855 (long)(c_can_read_reg_w(pchip, CCBT)));
856 CANMSG("Interrupt Register: 0x%.4lx\n",
857 (long)(c_can_read_reg_w(pchip, CCINTR)));
858 CANMSG("Test Register: 0x%.4lx\n",
859 (long)(c_can_read_reg_w(pchip, CCTR)));
860 CANMSG("Baud Rate Presc. Register: 0x%.4lx\n",
861 (long)(c_can_read_reg_w(pchip, CCBRPE)));
862 #ifdef C_CAN_WITH_CCCE
863 CANMSG("CAN Enable Register: 0x%.4lx\n",
864 (long)(c_can_read_reg_w(pchip, CCCE)));
866 CANMSG("Transm. Req. 1 Register: 0x%.4lx\n",
867 (long)(c_can_read_reg_w(pchip, CCTREQ1)));
868 CANMSG("Transm. Req. 2 Register: 0x%.4lx\n",
869 (long)(c_can_read_reg_w(pchip, CCTREQ2)));
870 CANMSG("New Data 1 Register: 0x%.4lx\n",
871 (long)(c_can_read_reg_w(pchip, CCND1)));
872 CANMSG("New Data 2 Register: 0x%.4lx\n",
873 (long)(c_can_read_reg_w(pchip, CCND2)));
874 CANMSG("Interrupt Pend. 1 Register: 0x%.4lx\n",
875 (long)(c_can_read_reg_w(pchip, CCINTP1)));
876 CANMSG("Interrupt Pend. 2 Register: 0x%.4lx\n",
877 (long)(c_can_read_reg_w(pchip, CCINTP2)));
878 CANMSG("------------------------------------\n");
879 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
880 (long)(c_can_read_reg_w(pchip, CCIF1CR)));
881 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
882 (long)(c_can_read_reg_w(pchip, CCIF1CM)));
883 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
884 (long)(c_can_read_reg_w(pchip, CCIF1M1)));
885 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
886 (long)(c_can_read_reg_w(pchip, CCIF1M2)));
887 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
888 (long)(c_can_read_reg_w(pchip, CCIF1A1)));
889 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
890 (long)(c_can_read_reg_w(pchip, CCIF1A2)));
891 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
892 (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
893 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
894 (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
895 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
896 (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
897 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
898 (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
899 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
900 (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
901 CANMSG("------------------------------------\n");
902 CANMSG("IF2 Command Req. Register: 0x%.4lx\n",
903 (long)(c_can_read_reg_w(pchip, CCIF2CR)));
904 CANMSG("IF2 Command Mask Register: 0x%.4lx\n",
905 (long)(c_can_read_reg_w(pchip, CCIF2CM)));
906 CANMSG("IF2 Mask 1 Register: 0x%.4lx\n",
907 (long)(c_can_read_reg_w(pchip, CCIF2M1)));
908 CANMSG("IF2 Mask 2 Register: 0x%.4lx\n",
909 (long)(c_can_read_reg_w(pchip, CCIF2M2)));
910 CANMSG("IF2 Arbitration 1 Register: 0x%.4lx\n",
911 (long)(c_can_read_reg_w(pchip, CCIF2A1)));
912 CANMSG("IF2 Arbitration 2 Register: 0x%.4lx\n",
913 (long)(c_can_read_reg_w(pchip, CCIF2A2)));
914 CANMSG("IF2 Message Control Register: 0x%.4lx\n",
915 (long)(c_can_read_reg_w(pchip, CCIF2DMC)));
916 CANMSG("IF2 Data A1 Register: 0x%.4lx\n",
917 (long)(c_can_read_reg_w(pchip, CCIF2DA1)));
918 CANMSG("IF2 Data A2 Register: 0x%.4lx\n",
919 (long)(c_can_read_reg_w(pchip, CCIF2DA2)));
920 CANMSG("IF2 Data B1 Register: 0x%.4lx\n",
921 (long)(c_can_read_reg_w(pchip, CCIF2DB1)));
922 CANMSG("IF2 Data B2 Register: 0x%.4lx\n",
923 (long)(c_can_read_reg_w(pchip, CCIF2DB2)));
924 CANMSG("------------------------------------\n");
925 CANMSG("------------------------------------\n");
928 void c_can_if1_registerdump(struct canchip_t *pchip)
930 CANMSG("----------------------------------------\n");
931 CANMSG("Error Counting Register: 0x%.4lx\n",
932 (long)(c_can_read_reg_w(pchip, CCEC)));
933 CANMSG("---------C-CAN IF1 Register Dump--------\n");
934 CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
935 (long)(c_can_read_reg_w(pchip, CCIF1CR)));
936 CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
937 (long)(c_can_read_reg_w(pchip, CCIF1CM)));
938 CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
939 (long)(c_can_read_reg_w(pchip, CCIF1M1)));
940 CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
941 (long)(c_can_read_reg_w(pchip, CCIF1M2)));
942 CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
943 (long)(c_can_read_reg_w(pchip, CCIF1A1)));
944 CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
945 (long)(c_can_read_reg_w(pchip, CCIF1A2)));
946 CANMSG("IF1 Message Control Register: 0x%.4lx\n",
947 (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
948 CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
949 (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
950 CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
951 (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
952 CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
953 (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
954 CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
955 (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
958 ///////////////////////////////////////////////////////////////////////
960 int c_can_register(struct chipspecops_t *chipspecops)
962 CANMSG("initializing c_can chip operations\n");
963 chipspecops->chip_config = c_can_chip_config;
964 chipspecops->baud_rate = c_can_baud_rate;
965 /*chipspecops->standard_mask=c_can_standard_mask;
966 chipspecops->extended_mask=c_can_extended_mask;
967 chipspecops->message15_mask=c_can_extended_mask; */
968 chipspecops->clear_objects = c_can_clear_objects;
969 /*chipspecops->config_irqs=c_can_config_irqs; */
970 chipspecops->pre_read_config = c_can_pre_read_config;
971 chipspecops->pre_write_config = c_can_pre_write_config;
972 chipspecops->send_msg = c_can_send_msg;
973 chipspecops->check_tx_stat = c_can_check_tx_stat;
974 chipspecops->wakeup_tx = c_can_wakeup_tx;
975 chipspecops->filtch_rq = c_can_filtch_rq;
976 chipspecops->remote_request = c_can_remote_request;
977 chipspecops->enable_configuration = c_can_enable_configuration;
978 chipspecops->disable_configuration = c_can_disable_configuration;
979 chipspecops->attach_to_chip = c_can_attach_to_chip;
980 chipspecops->release_chip = c_can_release_chip;
981 chipspecops->set_btregs = c_can_set_btregs;
982 chipspecops->start_chip = c_can_start_chip;
983 chipspecops->stop_chip = c_can_stop_chip;
984 chipspecops->irq_handler = c_can_irq_handler;
985 chipspecops->irq_accept = NULL;
989 int c_can_fill_chipspecops(struct canchip_t *chip)
991 chip->chip_type = "c_can";
992 if (MAX_MSGOBJS >= 32) {
993 chip->max_objects = 32;
995 CANMSG("C_CAN requires 32 message objects per chip,"
996 " but only %d is compiled maximum\n", MAX_MSGOBJS);
997 chip->max_objects = MAX_MSGOBJS;
999 c_can_register(chip->chipspecops);