jailhouse: configs: qemu and fiasco:
--reconfigure delay port on 0xed in qemu
--add pci devices for keyboard: ehci-usb
--remove virtion-9p-pci device form cfg
--enable 0x80 port back in fiasco. linux cell don't use it anymore.
Jan Kiszka [Tue, 1 Mar 2016 22:31:31 +0000 (23:31 +0100)]
x86: Unify AMD page tables for CPU and IOMMU
This exploits AMD's architecture feature that you can reuse the nested
page tables also for the IOMMU.
Both tables have the same depth (4), share the same address fields, the
valid bit - but all other bits are separate. Therefore, we need to
enhance the NPT paging handlers so that they fold both bit sets into an
entry.
The rewards are saving of several lines of code as well as a bunch of
hypervisor pages (typically some dozen).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Add iommu_pending_faults() for amd_iommu. This looks into
Hardware Event Register first, and then loops over the event log
printing what's in it. This way, we don't miss errors that happen
when event logging is unavailable.
Signed-off-by: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
[Jan: Cleanups] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Add functions to read event logs AMD IOMMU provides and print their
contents. The latter is rather basic, but decoding all possible log
entries is hairy, so we'd better wait and collect stats which
problems occur most often.
Jan Kiszka [Wed, 15 Jul 2015 19:34:47 +0000 (00:34 +0500)]
x86: Add iommu_commit_config() for amd_iommu
Implement functions to apply configuration for an IOMMU.
In case something goes wrong, we need to trigger an NMI, which
amd_iommu_init_fault_nmi() configures.
Based on patch by Valentine Sinitsyn.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Wed, 15 Jul 2015 19:13:05 +0000 (00:13 +0500)]
x86: Add device management functions for amd_iommu
Implement iommu_add_pci_device() for amd_iommu.
Basically, this is all about filling DTE entry. However, there is no way
to allocate device tables sparsely with ADM IOMMU. To save some memory,
Device Table Segmentation (Revision 2.6 and up) is used whenever possible,
and this adds some infrastructure.
Based on patch by Valentine Sinitsyn.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Add basic infrastructure (heavily influenced by Linux amd_iommu driver)
to submit commands to AMD IOMMU command buffer. For now, having only
INVALIDATE_IOMMU_PAGES and COMPLETION_WAIT seems to be sufficient.
Signed-off-by: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
[Jan: Cleanups, simplification of draining] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 1 Mar 2016 06:15:38 +0000 (07:15 +0100)]
x86: Extend bit range returned by x86_64_get_flags
In order to support also the AMD IOMMU with x86_64_paging, we extend
the set of bits returned by get_flags handler. We now include all bits
ignored by the MMU, which includes the bits relevant for the AMD IOMMU.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Fri, 13 Mar 2015 17:41:02 +0000 (22:41 +0500)]
core, configs, tools: Add AMD-specific fields to struct jailhouse_iommu
For AMD, we also need to store the PCI address, capability offset and
IOMMU feature bits coming from ACPI (overwriting what the hardware
reports) in the cell configuration file.
Based on patches by Valentine Sinitsyn.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Wed, 24 Feb 2016 09:19:54 +0000 (10:19 +0100)]
x86: Filter out physical address that can't be handled by DMAR units
Make sure that we do not try to program DMAR page tables with physical
addresses beyond the supported range (39 or 48 bits, depending on the
page table levels).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Sat, 20 Feb 2016 18:10:22 +0000 (19:10 +0100)]
x86: Account for DMAR units with multi-page register sets
The fault reporting registers we use may be placed in a 2nd or even 3rd
page. Account for such cases by using the MMIO region size now provided
via the system config.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Sat, 20 Feb 2016 18:09:49 +0000 (19:09 +0100)]
core, configs, tools: Prepare for variable IOMMU register set sizes
Introduce a size field to struct jailhouse_iommu and fill it via the
config generator. The information can be retrieved from the ACPI tables
for AMD. On Intel, we need to study the Linux mappings, thus we need to
demand that DMAR is enabled now while retrieving system information.
Based on patches by Valentine Sinitsyn.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
For both AMD and Intel, we need to store not only base address but also
a size to map the complete MMIO region. Moreover, AMD requires a number
of PCI device parameters for the IOMMU. Introduce struct jailhouse_iommu
that will encapsulate all required data.
Based on patches by Valentine Sinitsyn.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Wed, 3 Feb 2016 17:55:23 +0000 (18:55 +0100)]
inmates: e1000-demo: Enable queues explicitly
Newer NICs require us to enable the RX and TX queue. Although they
should be on after reset, at least the I350 refuses to work otherwise.
As the related bit is harmless or even unused on older NICs, do this
unconditionally (just like ipxe does).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 26 Jan 2016 08:27:40 +0000 (09:27 +0100)]
x86: Make debug UART port configurable via system config
We already allow to enable a VGA console via the system config, so let's
make the UART port configurable this way as well: phys_start will hold
the port, and flags must not have JAILHOUSE_MEM_IO set, in order to
differentiate us from the memory-mapped VGA console. And by leaving
phys_start at 0, we can even turn off the console now.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 25 Jan 2016 17:20:37 +0000 (18:20 +0100)]
core, driver: Pass rounded-up core size in hypervisor header
Hypervisor and root kernel may have different ideas about PAGE_SIZE.
This will cause wrong hypervisor core size calculations as seen on arm64
with 64K Linux PAGE_SIZE.
Avoid this trap by moving the round-up into the hypervisor code, passing
a ready-to-be-used size value in the header.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Daniel Sangorrin [Thu, 21 Jan 2016 01:31:26 +0000 (10:31 +0900)]
vga: Add support for VGA text buffer output on x86
Hypervisor messages are useful for debugging and are
typically handed out to the serial port. Unfortunately, x86
computers often lack of a serial port. This patch allows
hypervisor messages to be redirected to a screen by leveraging
the traditional VGA text buffer mode.
Signed-off-by: Daniel Sangorrin <daniel.sangorrin@toshiba.co.jp>
[Jan: avoid row_line writeback in panic case, remove redundant braces] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Sat, 9 Jan 2016 06:15:59 +0000 (07:15 +0100)]
configs: Update Banana Pi configs to make use of unaligned MMIO regions
Split up the MMIO page 0x1c20000 on the Alwinner A20 into CCU,
interrupts controller, GPIOs and the timer. GPIOs are further broken up
to allow assigning port H to the gic-demo cell, along with the CCU (to
control the UART timing).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Fri, 8 Jan 2016 18:18:34 +0000 (19:18 +0100)]
core: Add support for sub-page MMIO regions
This allows to specify memory regions for MMIO accesses that do not
start or end on page boundaries. Instead of mapping full pages into the
cell, sub-page MMIO requires to intercept the page accesses, validate
all parameters against the target memory region and then perform the
access in hypervisor context, provided the validation was successful.
As the access can now fail in hypervisor context, we need to be more
picky: besides read/write permissions, alignment and access widths can
be checked additionally. These attributes are specified via the
JAILHOUSE_MEM_IO_* flags.
Sub-page MMIO is surely not a fast path. It not only requires world
switches between cell and hypervisor, the current implementation also
uses dynamic mappings. This is easier to implement than a static mapping
scheme, but surely not faster. We may revisit this design later on,
ideally towards a 1:1 mapping scheme.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Thu, 7 Jan 2016 17:21:55 +0000 (18:21 +0100)]
core: Remove memory regions check
Most of the checks will be removed when adding sub-page memory region
support. We rather need some offline validation outside the hypervisor
eventually.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Thu, 7 Jan 2016 17:10:20 +0000 (18:10 +0100)]
arm: Remove useless warning from arm_mmio_perform_access
This functions is only called with size 1, 2 or 4. This is ensured by
arch_handle_dabt, the only (indirect) caller, which generates the size
accordingly (1 << sas) and filters out sizes > 4.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 11 Aug 2015 07:20:41 +0000 (09:20 +0200)]
configs: Add cache region to x86 demo cells
Assuming we have more than 4 units of L3 cache on systems that support
L3 partitioning, assign the first 2 units (e.g. 2 MB on a Xeon D 1540)
to apic-demo, the 3rd to tiny-demo. Also the non-root Linux config gets
the first 2 units (it cannot run in parallel to the other demos). All
this is for testing the management logic and will later be used to
benchmark the partitioning.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 11 Aug 2015 07:05:24 +0000 (09:05 +0200)]
x86: Introduce Cache Allocation Technology support for Intel CPUs
CAT is a CPU feature first added to Xeon D and certain Xeon E5 v3
processors. It so far allows to specify access restrictions to the L3
cache, including complete isolation between different entities.
This adds CAT control to Jailhouse on a per-cell level. The user is free
to specify a contiguous access mask for each cell, use that mask
exclusively (typical case), share any overlaps with the root cell
(JAILHOUSE_CACHE_ROOTSHARED), or simply use the root cell mask. If
nothing else is specified, the root cell uses the full cache (until
non-root cells shrink it).
Due to the hardware-induced requirement to have a contiguous bitmask,
shrinking the root mask on cell creation and extending it again on
destruction is not trivial. Not at all.
When creating a new cell, we may punch a hole into the root mask. In
that case, we also remove the lower half from the roor mask and
accumulate those bits in a "freed mask" for reuse once the hole closes
again. And if we are unlucky, adding a cell empties the current root
mask. Then we have to look into the freed mask and switch to it if it's
non-empty.
When restoring the root mask on cell destruction, we choose a simple
algorithm that first collects all released bits in the freed mask, then
try to merge that mask bit-wise with the current root cell mask. On
success we restart the freed mask walk to ensure that all contiguous
bits are merged.
One may wonder why not reallocating masks completely dynamically and
automatically on each reconfiguration, instead of requiring that
explicit allocation via the config? The reason is that we do not want to
invalidate cache allocations of those cells that are not involved in a
reconfiguration.
A lot of complication with this mechanism which looked so simple on
first sight. Let's just hope that there is a noteworthy benefit in
restricting CAT bitmasks in hardware this way.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 11 Aug 2015 06:58:38 +0000 (08:58 +0200)]
core, tools: Introduce cache regions to the cell configuration
Allow to specify regions of caches so that the hypervisor can partition
their usage accordingly whenever the hardware supports this.
The specification of their start location and sizes depend on the
architecture specific partitioning support. So far, only L3 cache types
are definable, either as unified cached or further partitioned into code
and data (to cater Intel's CAT and CDP). As with memory regions, caches
are usually taken from the root cell on non-root cell creation, but they
can also be declared as shared with the root cell.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Sun, 10 Jan 2016 08:42:43 +0000 (09:42 +0100)]
inmates: arm: Make LED blinking in gic-demo optional
This is both a test/demo case for command line parsing on ARM and a
feature to control the LED signal in the gic-demo on Banana Pi. The
green LED will now only blink if "blinking_led" is specified as inmate
command line option.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 4 Jan 2016 10:31:49 +0000 (11:31 +0100)]
inmates: x86: Add optional cache pollution to apic-demo
When "pollute_cache" is specified as command line parameter of the
apic-demo, the demo will fill each cache line with a pattern in each
measurement loop. Up to 512 KB of cache can be polluted this way.
This allows to test L3 cache partitioning features of recent Intel CPUs:
The cache pollution will dirty the L1 and L2 data caches so that the
next loop iteration will access L3. If that cache is shared, latencies
will rise as other cells use the cache as well.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 4 Jan 2016 10:28:08 +0000 (11:28 +0100)]
inmates: x86: Allow to bypass TSC and APIC timer calibration
Make use of the command line feature and introduce the "tsc_freq" and
"apic_freq" parameters. When provided, these values are used directly
instead of running calibrations against the PM timer.
This is particularly useful when running micro-benchmarks that are
sensitive to the inherent small variations of the calibrations.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 4 Jan 2016 10:25:09 +0000 (11:25 +0100)]
tools: jailhouse: Add support for string loading
Extend the "cell load" command by a variant where a string provided
along with the command is loaded into the cell memory. This can be used
together with the new command line feature to pass parameters to inmates
that support this.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Mon, 4 Jan 2016 10:17:11 +0000 (11:17 +0100)]
inmates: Add support for command line parameters
This provides support for parsing string, integer (long long type) and
boolean command line parameters. The former two need to be in the form
of "name=value" so that cmdline_parse_str/int will return the extracted
value. Boolean parameters are just of the form "name", and
cmdline_parse_bool will return true if this pattern is found. Parameters
need to be separated by blanks.
The parameters can be passed to the inmate by loading the string at an
architecture-specific location. That is 0xf0000 on x86 and 0x100 on ARM
so far. Note that the inmate has to reserve an appropriately sized
buffer via the CMDLINE_BUFFER macro.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
projects / jailhouse.git / log