x86: Unify AMD page tables for CPU and IOMMU

x86: Unify AMD page tables for CPU and IOMMU

This exploits AMD's architecture feature that you can reuse the nested
page tables also for the IOMMU.

Both tables have the same depth (4), share the same address fields, the
valid bit - but all other bits are separate. Therefore, we need to
enhance the NPT paging handlers so that they fold both bit sets into an
entry.

The rewards are saving of several lines of code as well as a bunch of
hypervisor pages (typically some dozen).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>