core, tools: Introduce cache regions to the cell configuration

Allow to specify regions of caches so that the hypervisor can partition
their usage accordingly whenever the hardware supports this.

The specification of their start location and sizes depend on the
architecture specific partitioning support. So far, only L3 cache types
are definable, either as unified cached or further partitioned into code
and data (to cater Intel's CAT and CDP). As with memory regions, caches
are usually taken from the root cell on non-root cell creation, but they
can also be declared as shared with the root cell.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/include/jailhouse/cell-config.h b/hypervisor/include/jailhouse/cell-config.h
index a6315a3012a7e2d7a08c90611bf24a6207be7287..a522b8d6414036d36c88e22dbc2b279ddcac0b98 100644 (file)
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -52,6 +52,7 @@ struct jailhouse_cell_desc {
 
        __u32 cpu_set_size;
        __u32 num_memory_regions;
+       __u32 num_cache_regions;
        __u32 num_irqchips;
        __u32 pio_bitmap_size;
        __u32 num_pci_devices;
@@ -83,6 +84,21 @@ struct jailhouse_memory {
        __u64 flags;
 } __attribute__((packed));
 
+#define JAILHOUSE_CACHE_L3_CODE                0x01
+#define JAILHOUSE_CACHE_L3_DATA                0x02
+#define JAILHOUSE_CACHE_L3             (JAILHOUSE_CACHE_L3_CODE | \
+                                        JAILHOUSE_CACHE_L3_DATA)
+
+#define JAILHOUSE_CACHE_ROOTSHARED     0x0001
+
+struct jailhouse_cache {
+       __u32 start;
+       __u32 size;
+       __u8 type;
+       __u8 padding;
+       __u16 flags;
+} __attribute__((packed));
+
 struct jailhouse_irqchip {
        __u64 address;
        __u64 id;
@@ -149,6 +165,7 @@ jailhouse_cell_config_size(struct jailhouse_cell_desc *cell)
        return sizeof(struct jailhouse_cell_desc) +
                cell->cpu_set_size +
                cell->num_memory_regions * sizeof(struct jailhouse_memory) +
+               cell->num_cache_regions * sizeof(struct jailhouse_cache) +
                cell->num_irqchips * sizeof(struct jailhouse_irqchip) +
                cell->pio_bitmap_size +
                cell->num_pci_devices * sizeof(struct jailhouse_pci_device) +
@@ -176,12 +193,20 @@ jailhouse_cell_mem_regions(const struct jailhouse_cell_desc *cell)
                ((void *)jailhouse_cell_cpu_set(cell) + cell->cpu_set_size);
 }
 
+static inline const struct jailhouse_cache *
+jailhouse_cell_cache_regions(const struct jailhouse_cell_desc *cell)
+{
+       return (const struct jailhouse_cache *)
+               ((void *)jailhouse_cell_mem_regions(cell) +
+                cell->num_memory_regions * sizeof(struct jailhouse_memory));
+}
+
 static inline const struct jailhouse_irqchip *
 jailhouse_cell_irqchips(const struct jailhouse_cell_desc *cell)
 {
        return (const struct jailhouse_irqchip *)
-               ((void *)jailhouse_cell_mem_regions(cell) +
-                cell->num_memory_regions * sizeof(struct jailhouse_memory));
+               ((void *)jailhouse_cell_cache_regions(cell) +
+                cell->num_cache_regions * sizeof(struct jailhouse_cache));
 }
 
 static inline const __u8 *

diff --git a/tools/jailhouse-cell-linux b/tools/jailhouse-cell-linux
index a6d738c65023cb54f96a7f2b242a1e2dd13a966c..02f47cd9c498b75165ac5dbde2462d3be1409479 100755 (executable)
--- a/tools/jailhouse-cell-linux
+++ b/tools/jailhouse-cell-linux
@@ -69,7 +69,7 @@ class MemoryRegion:
 
 
 class Config:
-    _HEADER_FORMAT = '8x32sIIIIIII'
+    _HEADER_FORMAT = '8x32sIIIIIIII'
 
     def __init__(self, config_file):
         self.data = config_file.read()
@@ -78,6 +78,7 @@ class Config:
          self.flags,
          self.cpu_set_size,
          self.num_memory_regions,
+         self.num_cache_regions,
          self.num_irqchips,
          self.pio_bitmap_size,
          self.num_pci_devices,