arm: Fix byte-wise write access to GICD_ITARGETSRn

While expanding byte accesses to full words, we forgot to adjust the
address as well. This led to unaligned word accesses on writes, followed
by hypervisor aborts.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/arm/gic-common.c b/hypervisor/arch/arm/gic-common.c
index a8ac4c7efb1ffe052f80597ff5ae879e3640d29b..51f6bee02c431d6d0331addb9f279f1b77bc0b33 100644 (file)
--- a/hypervisor/arch/arm/gic-common.c
+++ b/hypervisor/arch/arm/gic-common.c
@@ -167,10 +167,10 @@ static enum mmio_result handle_irq_target(struct mmio_access *mmio,
        }
 
        /*
-        * The registers are byte-accessible, extend the access to a word if
-        * necessary.
+        * The registers are byte-accessible, but we always do word accesses.
         */
        offset = spi % 4;
+       mmio->address &= ~0x3;
        mmio->value <<= 8 * offset;
        mmio->size = 4;
        spi -= offset;