From: Jan Kiszka <jan.kiszka@siemens.com>
Date: Thu, 23 Jun 2016 06:31:02 +0000 (+0200)
Subject: arm: Fix byte-wise write access to GICD_ITARGETSRn
X-Git-Url: http://rtime.felk.cvut.cz/gitweb/jailhouse.git/commitdiff_plain/bf96fe4922710b75cc4c28022d3235fda83c1bf3

arm: Fix byte-wise write access to GICD_ITARGETSRn

While expanding byte accesses to full words, we forgot to adjust the
address as well. This led to unaligned word accesses on writes, followed
by hypervisor aborts.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---

diff --git a/hypervisor/arch/arm/gic-common.c b/hypervisor/arch/arm/gic-common.c
index a8ac4c7..51f6bee 100644
--- a/hypervisor/arch/arm/gic-common.c
+++ b/hypervisor/arch/arm/gic-common.c
@@ -167,10 +167,10 @@ static enum mmio_result handle_irq_target(struct mmio_access *mmio,
 	}
 
 	/*
-	 * The registers are byte-accessible, extend the access to a word if
-	 * necessary.
+	 * The registers are byte-accessible, but we always do word accesses.
 	 */
 	offset = spi % 4;
+	mmio->address &= ~0x3;
 	mmio->value <<= 8 * offset;
 	mmio->size = 4;
 	spi -= offset;