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arm: Fix byte-wise write access to GICD_ITARGETSRn
authorJan Kiszka <jan.kiszka@siemens.com>
Thu, 23 Jun 2016 06:31:02 +0000 (08:31 +0200)
committerJan Kiszka <jan.kiszka@siemens.com>
Sun, 26 Jun 2016 07:16:27 +0000 (09:16 +0200)
commitbf96fe4922710b75cc4c28022d3235fda83c1bf3
tree48e5c336b9a3259ca64fa06303919afac70e7b78tree | snapshot
parentd747205eec4bb66e95b1de426d618a8c6d34d61acommit | diff
arm: Fix byte-wise write access to GICD_ITARGETSRn

While expanding byte accesses to full words, we forgot to adjust the
address as well. This led to unaligned word accesses on writes, followed
by hypervisor aborts.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
hypervisor/arch/arm/gic-common.c diff | blob | history