hypervisor/arch/x86/svm.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  * Copyright (c) Valentine Sinitsyn, 2014
   6  *
   7  * Authors:
   8  *  Jan Kiszka <jan.kiszka@siemens.com>
   9  *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  10  *
  11  * Based on vmx.c written by Jan Kiszka.
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  */
  16
  17 #include <jailhouse/entry.h>
  18 #include <jailhouse/cell-config.h>
  19 #include <jailhouse/control.h>
  20 #include <jailhouse/paging.h>
  21 #include <jailhouse/printk.h>
  22 #include <jailhouse/processor.h>
  23 #include <jailhouse/string.h>
  24 #include <jailhouse/utils.h>
  25 #include <asm/apic.h>
  26 #include <asm/cell.h>
  27 #include <asm/control.h>
  28 #include <asm/iommu.h>
  29 #include <asm/paging.h>
  30 #include <asm/percpu.h>
  31 #include <asm/processor.h>
  32 #include <asm/svm.h>
  33 #include <asm/vcpu.h>
  34
  35 /*
  36  * NW bit is ignored by all modern processors, however some
  37  * combinations of NW and CD bits are prohibited by SVM (see APMv2,
  38  * Sect. 15.5). To handle this, we always keep the NW bit off.
  39  */
  40 #define SVM_CR0_ALLOWED_BITS    (~X86_CR0_NW)
  41
  42 #define MTRR_DEFTYPE            0x2ff
  43
  44 static bool has_avic, has_assists, has_flush_by_asid;
  45
  46 static const struct segment invalid_seg;
  47
  48 static struct paging npt_paging[NPT_PAGE_DIR_LEVELS];
  49
  50 /* bit cleared: direct access allowed */
  51 // TODO: convert to whitelist
  52 static u8 __attribute__((aligned(PAGE_SIZE))) msrpm[][0x2000/4] = {
  53         [ SVM_MSRPM_0000 ] = {
  54                 [      0/4 ...  0x017/4 ] = 0,
  55                 [  0x018/4 ...  0x01b/4 ] = 0x80, /* 0x01b (w) */
  56                 [  0x01c/4 ...  0x273/4 ] = 0,
  57                 [  0x274/4 ...  0x277/4 ] = 0xc0, /* 0x277 (rw) */
  58                 [  0x278/4 ...  0x2fb/4 ] = 0,
  59                 [  0x2fc/4 ...  0x2ff/4 ] = 0x80, /* 0x2ff (w) */
  60                 [  0x300/4 ...  0x7ff/4 ] = 0,
  61                 /* x2APIC MSRs - emulated if not present */
  62                 [  0x800/4 ...  0x803/4 ] = 0x90, /* 0x802 (r), 0x803 (r) */
  63                 [  0x804/4 ...  0x807/4 ] = 0,
  64                 [  0x808/4 ...  0x80b/4 ] = 0x93, /* 0x808 (rw), 0x80a (r), 0x80b (w) */
  65                 [  0x80c/4 ...  0x80f/4 ] = 0xc8, /* 0x80d (w), 0x80f (rw) */
  66                 [  0x810/4 ...  0x813/4 ] = 0x55, /* 0x810 - 0x813 (r) */
  67                 [  0x814/4 ...  0x817/4 ] = 0x55, /* 0x814 - 0x817 (r) */
  68                 [  0x818/4 ...  0x81b/4 ] = 0x55, /* 0x818 - 0x81b (r) */
  69                 [  0x81c/4 ...  0x81f/4 ] = 0x55, /* 0x81c - 0x81f (r) */
  70                 [  0x820/4 ...  0x823/4 ] = 0x55, /* 0x820 - 0x823 (r) */
  71                 [  0x824/4 ...  0x827/4 ] = 0x55, /* 0x823 - 0x827 (r) */
  72                 [  0x828/4 ...  0x82b/4 ] = 0x03, /* 0x828 (rw) */
  73                 [  0x82c/4 ...  0x82f/4 ] = 0xc0, /* 0x82f (rw) */
  74                 [  0x830/4 ...  0x833/4 ] = 0xf3, /* 0x830 (rw), 0x832 (rw), 0x833 (rw) */
  75                 [  0x834/4 ...  0x837/4 ] = 0xff, /* 0x834 - 0x837 (rw) */
  76                 [  0x838/4 ...  0x83b/4 ] = 0x07, /* 0x838 (rw), 0x839 (r) */
  77                 [  0x83c/4 ...  0x83f/4 ] = 0x70, /* 0x83e (rw), 0x83f (r) */
  78                 [  0x840/4 ... 0x1fff/4 ] = 0,
  79         },
  80         [ SVM_MSRPM_C000 ] = {
  81                 [      0/4 ...  0x07f/4 ] = 0,
  82                 [  0x080/4 ...  0x083/4 ] = 0x02, /* 0x080 (w) */
  83                 [  0x084/4 ... 0x1fff/4 ] = 0
  84         },
  85         [ SVM_MSRPM_C001 ] = {
  86                 [      0/4 ... 0x1fff/4 ] = 0,
  87         },
  88         [ SVM_MSRPM_RESV ] = {
  89                 [      0/4 ... 0x1fff/4 ] = 0,
  90         }
  91 };
  92
  93 /* This page is mapped so the code begins at 0x000ffff0 */
  94 static u8 __attribute__((aligned(PAGE_SIZE))) parking_code[PAGE_SIZE] = {
  95         [0xff0] = 0xfa, /* 1: cli */
  96         [0xff1] = 0xf4, /*    hlt */
  97         [0xff2] = 0xeb,
  98         [0xff3] = 0xfc  /*    jmp 1b */
  99 };
 100
 101 static void *parked_mode_npt;
 102
 103 static void *avic_page;
 104
 105 static int svm_check_features(void)
 106 {
 107         /* SVM is available */
 108         if (!(cpuid_ecx(0x80000001) & X86_FEATURE_SVM))
 109                 return trace_error(-ENODEV);
 110
 111         /* Nested paging */
 112         if (!(cpuid_edx(0x8000000A) & X86_FEATURE_NP))
 113                 return trace_error(-EIO);
 114
 115         /* Decode assists */
 116         if ((cpuid_edx(0x8000000A) & X86_FEATURE_DECODE_ASSISTS))
 117                 has_assists = true;
 118
 119         /* AVIC support */
 120         if (cpuid_edx(0x8000000A) & X86_FEATURE_AVIC)
 121                 has_avic = true;
 122
 123         /* TLB Flush by ASID support */
 124         if (cpuid_edx(0x8000000A) & X86_FEATURE_FLUSH_BY_ASID)
 125                 has_flush_by_asid = true;
 126
 127         return 0;
 128 }
 129
 130 static void set_svm_segment_from_dtr(struct svm_segment *svm_segment,
 131                                      const struct desc_table_reg *dtr)
 132 {
 133         struct svm_segment tmp = { 0 };
 134
 135         if (dtr) {
 136                 tmp.base = dtr->base;
 137                 tmp.limit = dtr->limit & 0xffff;
 138         }
 139
 140         *svm_segment = tmp;
 141 }
 142
 143 /* TODO: struct segment needs to be x86 generic, not VMX-specific one here */
 144 static void set_svm_segment_from_segment(struct svm_segment *svm_segment,
 145                                          const struct segment *segment)
 146 {
 147         u32 ar;
 148
 149         svm_segment->selector = segment->selector;
 150
 151         if (segment->access_rights == 0x10000) {
 152                 svm_segment->access_rights = 0;
 153         } else {
 154                 ar = segment->access_rights;
 155                 svm_segment->access_rights =
 156                         ((ar & 0xf000) >> 4) | (ar & 0x00ff);
 157         }
 158
 159         svm_segment->limit = segment->limit;
 160         svm_segment->base = segment->base;
 161 }
 162
 163 static bool svm_set_cell_config(struct cell *cell, struct vmcb *vmcb)
 164 {
 165         /* No real need for this function; used for consistency with vmx.c */
 166         vmcb->iopm_base_pa = paging_hvirt2phys(cell->svm.iopm);
 167         vmcb->n_cr3 = paging_hvirt2phys(cell->svm.npt_structs.root_table);
 168
 169         return true;
 170 }
 171
 172 static int vmcb_setup(struct per_cpu *cpu_data)
 173 {
 174         struct vmcb *vmcb = &cpu_data->vmcb;
 175
 176         memset(vmcb, 0, sizeof(struct vmcb));
 177
 178         vmcb->cr0 = cpu_data->linux_cr0 & SVM_CR0_ALLOWED_BITS;
 179         vmcb->cr3 = cpu_data->linux_cr3;
 180         vmcb->cr4 = cpu_data->linux_cr4;
 181
 182         set_svm_segment_from_segment(&vmcb->cs, &cpu_data->linux_cs);
 183         set_svm_segment_from_segment(&vmcb->ds, &cpu_data->linux_ds);
 184         set_svm_segment_from_segment(&vmcb->es, &cpu_data->linux_es);
 185         set_svm_segment_from_segment(&vmcb->fs, &cpu_data->linux_fs);
 186         set_svm_segment_from_segment(&vmcb->gs, &cpu_data->linux_gs);
 187         set_svm_segment_from_segment(&vmcb->ss, &invalid_seg);
 188         set_svm_segment_from_segment(&vmcb->tr, &cpu_data->linux_tss);
 189
 190         set_svm_segment_from_dtr(&vmcb->ldtr, NULL);
 191         set_svm_segment_from_dtr(&vmcb->gdtr, &cpu_data->linux_gdtr);
 192         set_svm_segment_from_dtr(&vmcb->idtr, &cpu_data->linux_idtr);
 193
 194         vmcb->cpl = 0; /* Linux runs in ring 0 before migration */
 195
 196         vmcb->rflags = 0x02;
 197         /* Indicate success to the caller of arch_entry */
 198         vmcb->rax = 0;
 199         vmcb->rsp = cpu_data->linux_sp +
 200                 (NUM_ENTRY_REGS + 1) * sizeof(unsigned long);
 201         vmcb->rip = cpu_data->linux_ip;
 202
 203         vmcb->sysenter_cs = read_msr(MSR_IA32_SYSENTER_CS);
 204         vmcb->sysenter_eip = read_msr(MSR_IA32_SYSENTER_EIP);
 205         vmcb->sysenter_esp = read_msr(MSR_IA32_SYSENTER_ESP);
 206         vmcb->star = read_msr(MSR_STAR);
 207         vmcb->lstar = read_msr(MSR_LSTAR);
 208         vmcb->cstar = read_msr(MSR_CSTAR);
 209         vmcb->sfmask = read_msr(MSR_SFMASK);
 210         vmcb->kerngsbase = read_msr(MSR_KERNGS_BASE);
 211
 212         vmcb->dr6 = 0x00000ff0;
 213         vmcb->dr7 = 0x00000400;
 214
 215         /* Make the hypervisor visible */
 216         vmcb->efer = (cpu_data->linux_efer | EFER_SVME);
 217
 218         /* Linux uses custom PAT setting */
 219         vmcb->g_pat = cpu_data->linux_pat;
 220
 221         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_NMI;
 222         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CR0_SEL_WRITE;
 223         /* TODO: Do we need this for SVM ? */
 224         /* vmcb->general1_intercepts |= GENERAL1_INTERCEPT_CPUID; */
 225         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_IOIO_PROT;
 226         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_MSR_PROT;
 227         vmcb->general1_intercepts |= GENERAL1_INTERCEPT_SHUTDOWN_EVT;
 228
 229         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMRUN; /* Required */
 230         vmcb->general2_intercepts |= GENERAL2_INTERCEPT_VMMCALL;
 231
 232         vmcb->msrpm_base_pa = paging_hvirt2phys(msrpm);
 233
 234         vmcb->np_enable = 1;
 235         /* No more than one guest owns the CPU */
 236         vmcb->guest_asid = 1;
 237
 238         /* TODO: Setup AVIC */
 239
 240         /* Explicitly mark all of the state as new */
 241         vmcb->clean_bits = 0;
 242
 243         return svm_set_cell_config(cpu_data->cell, vmcb);
 244 }
 245
 246 unsigned long arch_paging_gphys2phys(struct per_cpu *cpu_data,
 247                                      unsigned long gphys,
 248                                      unsigned long flags)
 249 {
 250         return paging_virt2phys(&cpu_data->cell->svm.npt_structs,
 251                         gphys, flags);
 252 }
 253
 254 static void npt_set_next_pt(pt_entry_t pte, unsigned long next_pt)
 255 {
 256         /* See APMv2, Section 15.25.5 */
 257         *pte = (next_pt & 0x000ffffffffff000UL) |
 258                 (PAGE_DEFAULT_FLAGS | PAGE_FLAG_US);
 259 }
 260
 261 int vcpu_vendor_init(void)
 262 {
 263         struct paging_structures parking_pt;
 264         unsigned long vm_cr;
 265         int err, n;
 266
 267         err = svm_check_features();
 268         if (err)
 269                 return err;
 270
 271         vm_cr = read_msr(MSR_VM_CR);
 272         if (vm_cr & VM_CR_SVMDIS)
 273                 /* SVM disabled in BIOS */
 274                 return trace_error(-EPERM);
 275
 276         /* Nested paging is the same as the native one */
 277         memcpy(npt_paging, x86_64_paging, sizeof(npt_paging));
 278         for (n = 0; n < NPT_PAGE_DIR_LEVELS; n++)
 279                 npt_paging[n].set_next_pt = npt_set_next_pt;
 280
 281         /* Map guest parking code (shared between cells and CPUs) */
 282         parking_pt.root_paging = npt_paging;
 283         parking_pt.root_table = parked_mode_npt = page_alloc(&mem_pool, 1);
 284         if (!parked_mode_npt)
 285                 return -ENOMEM;
 286         err = paging_create(&parking_pt, paging_hvirt2phys(parking_code),
 287                             PAGE_SIZE, 0x000ff000,
 288                             PAGE_READONLY_FLAGS | PAGE_FLAG_US,
 289                             PAGING_NON_COHERENT);
 290         if (err)
 291                 return err;
 292
 293         /* This is always false for AMD now (except in nested SVM);
 294            see Sect. 16.3.1 in APMv2 */
 295         if (using_x2apic) {
 296                 /* allow direct x2APIC access except for ICR writes */
 297                 memset(&msrpm[SVM_MSRPM_0000][MSR_X2APIC_BASE/4], 0,
 298                                 (MSR_X2APIC_END - MSR_X2APIC_BASE + 1)/4);
 299                 msrpm[SVM_MSRPM_0000][MSR_X2APIC_ICR/4] = 0x02;
 300         } else {
 301                 if (has_avic) {
 302                         avic_page = page_alloc(&remap_pool, 1);
 303                         if (!avic_page)
 304                                 return trace_error(-ENOMEM);
 305                 }
 306         }
 307
 308         return vcpu_cell_init(&root_cell);
 309 }
 310
 311 int vcpu_vendor_cell_init(struct cell *cell)
 312 {
 313         u64 flags;
 314         int err;
 315
 316         /* allocate iopm (two 4-K pages + 3 bits) */
 317         cell->svm.iopm = page_alloc(&mem_pool, 3);
 318         if (!cell->svm.iopm)
 319                 return -ENOMEM;
 320
 321         /* build root NPT of cell */
 322         cell->svm.npt_structs.root_paging = npt_paging;
 323         cell->svm.npt_structs.root_table = page_alloc(&mem_pool, 1);
 324         if (!cell->svm.npt_structs.root_table)
 325                 return -ENOMEM;
 326
 327         if (!has_avic) {
 328                 /*
 329                  * Map xAPIC as is; reads are passed, writes are trapped.
 330                  */
 331                 flags = PAGE_READONLY_FLAGS | PAGE_FLAG_US | PAGE_FLAG_DEVICE;
 332                 err = paging_create(&cell->svm.npt_structs, XAPIC_BASE,
 333                                     PAGE_SIZE, XAPIC_BASE,
 334                                     flags,
 335                                     PAGING_NON_COHERENT);
 336         } else {
 337                 flags = PAGE_DEFAULT_FLAGS | PAGE_FLAG_DEVICE;
 338                 err = paging_create(&cell->svm.npt_structs,
 339                                     paging_hvirt2phys(avic_page),
 340                                     PAGE_SIZE, XAPIC_BASE,
 341                                     flags,
 342                                     PAGING_NON_COHERENT);
 343         }
 344
 345         return err;
 346 }
 347
 348 int vcpu_map_memory_region(struct cell *cell,
 349                            const struct jailhouse_memory *mem)
 350 {
 351         u64 phys_start = mem->phys_start;
 352         u64 flags = PAGE_FLAG_US; /* See APMv2, Section 15.25.5 */
 353
 354         if (mem->flags & JAILHOUSE_MEM_READ)
 355                 flags |= PAGE_FLAG_PRESENT;
 356         if (mem->flags & JAILHOUSE_MEM_WRITE)
 357                 flags |= PAGE_FLAG_RW;
 358         if (!(mem->flags & JAILHOUSE_MEM_EXECUTE))
 359                 flags |= PAGE_FLAG_NOEXECUTE;
 360         if (mem->flags & JAILHOUSE_MEM_COMM_REGION)
 361                 phys_start = paging_hvirt2phys(&cell->comm_page);
 362
 363         return paging_create(&cell->svm.npt_structs, phys_start, mem->size,
 364                              mem->virt_start, flags, PAGING_NON_COHERENT);
 365 }
 366
 367 int vcpu_unmap_memory_region(struct cell *cell,
 368                              const struct jailhouse_memory *mem)
 369 {
 370         return paging_destroy(&cell->svm.npt_structs, mem->virt_start,
 371                               mem->size, PAGING_NON_COHERENT);
 372 }
 373
 374 void vcpu_vendor_cell_exit(struct cell *cell)
 375 {
 376         paging_destroy(&cell->svm.npt_structs, XAPIC_BASE, PAGE_SIZE,
 377                        PAGING_NON_COHERENT);
 378         page_free(&mem_pool, cell->svm.npt_structs.root_table, 1);
 379 }
 380
 381 int vcpu_init(struct per_cpu *cpu_data)
 382 {
 383         unsigned long efer;
 384         int err;
 385
 386         err = svm_check_features();
 387         if (err)
 388                 return err;
 389
 390         efer = read_msr(MSR_EFER);
 391         if (efer & EFER_SVME)
 392                 return trace_error(-EBUSY);
 393
 394         efer |= EFER_SVME;
 395         write_msr(MSR_EFER, efer);
 396
 397         cpu_data->svm_state = SVMON;
 398
 399         if (!vmcb_setup(cpu_data))
 400                 return trace_error(-EIO);
 401
 402         /*
 403          * APM Volume 2, 3.1.1: "When writing the CR0 register, software should
 404          * set the values of reserved bits to the values found during the
 405          * previous CR0 read."
 406          * But we want to avoid surprises with new features unknown to us but
 407          * set by Linux. So check if any assumed revered bit was set and bail
 408          * out if so.
 409          * Note that the APM defines all reserved CR4 bits as must-be-zero.
 410          */
 411         if (cpu_data->linux_cr0 & X86_CR0_RESERVED)
 412                 return -EIO;
 413
 414         /* bring CR0 and CR4 into well-defined states */
 415         write_cr0(X86_CR0_HOST_STATE);
 416         write_cr4(X86_CR4_HOST_STATE);
 417
 418         write_msr(MSR_VM_HSAVE_PA, paging_hvirt2phys(cpu_data->host_state));
 419
 420         return 0;
 421 }
 422
 423 void vcpu_exit(struct per_cpu *cpu_data)
 424 {
 425         unsigned long efer;
 426
 427         if (cpu_data->svm_state == SVMOFF)
 428                 return;
 429
 430         cpu_data->svm_state = SVMOFF;
 431
 432         /* We are leaving - set the GIF */
 433         asm volatile ("stgi" : : : "memory");
 434
 435         efer = read_msr(MSR_EFER);
 436         efer &= ~EFER_SVME;
 437         write_msr(MSR_EFER, efer);
 438
 439         write_msr(MSR_VM_HSAVE_PA, 0);
 440 }
 441
 442 void __attribute__((noreturn)) vcpu_activate_vmm(struct per_cpu *cpu_data)
 443 {
 444         unsigned long vmcb_pa, host_stack;
 445
 446         vmcb_pa = paging_hvirt2phys(&cpu_data->vmcb);
 447         host_stack = (unsigned long)cpu_data->stack + sizeof(cpu_data->stack);
 448
 449         /* We enter Linux at the point arch_entry would return to as well.
 450          * rax is cleared to signal success to the caller. */
 451         asm volatile(
 452                 "clgi\n\t"
 453                 "mov (%%rdi),%%r15\n\t"
 454                 "mov 0x8(%%rdi),%%r14\n\t"
 455                 "mov 0x10(%%rdi),%%r13\n\t"
 456                 "mov 0x18(%%rdi),%%r12\n\t"
 457                 "mov 0x20(%%rdi),%%rbx\n\t"
 458                 "mov 0x28(%%rdi),%%rbp\n\t"
 459                 "mov %0, %%rax\n\t"
 460                 "vmload %%rax\n\t"
 461                 "vmrun %%rax\n\t"
 462                 "vmsave %%rax\n\t"
 463                 /* Restore hypervisor stack */
 464                 "mov %2, %%rsp\n\t"
 465                 "jmp svm_vmexit"
 466                 : /* no output */
 467                 : "m" (vmcb_pa), "D" (cpu_data->linux_reg), "m" (host_stack)
 468                 : "memory", "r15", "r14", "r13", "r12",
 469                   "rbx", "rbp", "rax", "cc");
 470         __builtin_unreachable();
 471 }
 472
 473 void __attribute__((noreturn))
 474 vcpu_deactivate_vmm(struct registers *guest_regs)
 475 {
 476         struct per_cpu *cpu_data = this_cpu_data();
 477         struct vmcb *vmcb = &cpu_data->vmcb;
 478         unsigned long *stack = (unsigned long *)vmcb->rsp;
 479         unsigned long linux_ip = vmcb->rip;
 480
 481         /*
 482          * Restore the MSRs.
 483          *
 484          * XXX: One could argue this is better to be done in
 485          * arch_cpu_restore(), however, it would require changes
 486          * to cpu_data to store STAR and friends.
 487          */
 488         write_msr(MSR_STAR, vmcb->star);
 489         write_msr(MSR_LSTAR, vmcb->lstar);
 490         write_msr(MSR_CSTAR, vmcb->cstar);
 491         write_msr(MSR_SFMASK, vmcb->sfmask);
 492         write_msr(MSR_KERNGS_BASE, vmcb->kerngsbase);
 493
 494         cpu_data->linux_cr0 = vmcb->cr0;
 495         cpu_data->linux_cr3 = vmcb->cr3;
 496
 497         cpu_data->linux_gdtr.base = vmcb->gdtr.base;
 498         cpu_data->linux_gdtr.limit = vmcb->gdtr.limit;
 499         cpu_data->linux_idtr.base = vmcb->idtr.base;
 500         cpu_data->linux_idtr.limit = vmcb->idtr.limit;
 501
 502         cpu_data->linux_cs.selector = vmcb->cs.selector;
 503
 504         cpu_data->linux_tss.selector = vmcb->tr.selector;
 505
 506         cpu_data->linux_pat = vmcb->g_pat;
 507         cpu_data->linux_efer = vmcb->efer & (~EFER_SVME);
 508         cpu_data->linux_fs.base = vmcb->fs.base;
 509         cpu_data->linux_gs.base = vmcb->gs.base;
 510
 511         cpu_data->linux_sysenter_cs = vmcb->sysenter_cs;
 512         cpu_data->linux_sysenter_eip = vmcb->sysenter_eip;
 513         cpu_data->linux_sysenter_esp = vmcb->sysenter_esp;
 514
 515         cpu_data->linux_ds.selector = vmcb->ds.selector;
 516         cpu_data->linux_es.selector = vmcb->es.selector;
 517         cpu_data->linux_fs.selector = vmcb->fs.selector;
 518         cpu_data->linux_gs.selector = vmcb->gs.selector;
 519
 520         arch_cpu_restore(cpu_data, 0);
 521
 522         stack--;
 523         *stack = linux_ip;
 524
 525         asm volatile (
 526                 "mov %%rbx,%%rsp\n\t"
 527                 "pop %%r15\n\t"
 528                 "pop %%r14\n\t"
 529                 "pop %%r13\n\t"
 530                 "pop %%r12\n\t"
 531                 "pop %%r11\n\t"
 532                 "pop %%r10\n\t"
 533                 "pop %%r9\n\t"
 534                 "pop %%r8\n\t"
 535                 "pop %%rdi\n\t"
 536                 "pop %%rsi\n\t"
 537                 "pop %%rbp\n\t"
 538                 "add $8,%%rsp\n\t"
 539                 "pop %%rbx\n\t"
 540                 "pop %%rdx\n\t"
 541                 "pop %%rcx\n\t"
 542                 "mov %%rax,%%rsp\n\t"
 543                 "xor %%rax,%%rax\n\t"
 544                 "ret"
 545                 : : "a" (stack), "b" (guest_regs));
 546         __builtin_unreachable();
 547 }
 548
 549 static void svm_vcpu_reset(struct per_cpu *cpu_data, unsigned int sipi_vector)
 550 {
 551         struct vmcb *vmcb = &cpu_data->vmcb;
 552         unsigned long val;
 553         bool ok = true;
 554
 555         vmcb->cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 556         vmcb->cr3 = 0;
 557         vmcb->cr4 = 0;
 558
 559         vmcb->rflags = 0x02;
 560
 561         val = 0;
 562         if (sipi_vector == APIC_BSP_PSEUDO_SIPI) {
 563                 val = 0xfff0;
 564                 sipi_vector = 0xf0;
 565         }
 566         vmcb->rip = val;
 567         vmcb->rsp = 0;
 568
 569         vmcb->cs.selector = sipi_vector << 8;
 570         vmcb->cs.base = sipi_vector << 12;
 571         vmcb->cs.limit = 0xffff;
 572         vmcb->cs.access_rights = 0x009b;
 573
 574         vmcb->ds.selector = 0;
 575         vmcb->ds.base = 0;
 576         vmcb->ds.limit = 0xffff;
 577         vmcb->ds.access_rights = 0x0093;
 578
 579         vmcb->es.selector = 0;
 580         vmcb->es.base = 0;
 581         vmcb->es.limit = 0xffff;
 582         vmcb->es.access_rights = 0x0093;
 583
 584         vmcb->fs.selector = 0;
 585         vmcb->fs.base = 0;
 586         vmcb->fs.limit = 0xffff;
 587         vmcb->fs.access_rights = 0x0093;
 588
 589         vmcb->gs.selector = 0;
 590         vmcb->gs.base = 0;
 591         vmcb->gs.limit = 0xffff;
 592         vmcb->gs.access_rights = 0x0093;
 593
 594         vmcb->ss.selector = 0;
 595         vmcb->ss.base = 0;
 596         vmcb->ss.limit = 0xffff;
 597         vmcb->ss.access_rights = 0x0093;
 598
 599         vmcb->tr.selector = 0;
 600         vmcb->tr.base = 0;
 601         vmcb->tr.limit = 0xffff;
 602         vmcb->tr.access_rights = 0x008b;
 603
 604         vmcb->ldtr.selector = 0;
 605         vmcb->ldtr.base = 0;
 606         vmcb->ldtr.limit = 0xffff;
 607         vmcb->ldtr.access_rights = 0x0082;
 608
 609         vmcb->gdtr.selector = 0;
 610         vmcb->gdtr.base = 0;
 611         vmcb->gdtr.limit = 0xffff;
 612         vmcb->gdtr.access_rights = 0;
 613
 614         vmcb->idtr.selector = 0;
 615         vmcb->idtr.base = 0;
 616         vmcb->idtr.limit = 0xffff;
 617         vmcb->idtr.access_rights = 0;
 618
 619         vmcb->efer = EFER_SVME;
 620
 621         /* These MSRs are undefined on reset */
 622         vmcb->star = 0;
 623         vmcb->lstar = 0;
 624         vmcb->cstar = 0;
 625         vmcb->sfmask = 0;
 626         vmcb->sysenter_cs = 0;
 627         vmcb->sysenter_eip = 0;
 628         vmcb->sysenter_esp = 0;
 629         vmcb->kerngsbase = 0;
 630
 631         vmcb->g_pat = PAT_RESET_VALUE;
 632
 633         vmcb->dr7 = 0x00000400;
 634
 635         /* Almost all of the guest state changed */
 636         vmcb->clean_bits = 0;
 637
 638         ok &= svm_set_cell_config(cpu_data->cell, vmcb);
 639
 640         /* This is always false, but to be consistent with vmx.c... */
 641         if (!ok) {
 642                 panic_printk("FATAL: CPU reset failed\n");
 643                 panic_stop();
 644         }
 645 }
 646
 647 void vcpu_skip_emulated_instruction(unsigned int inst_len)
 648 {
 649         struct per_cpu *cpu_data = this_cpu_data();
 650         struct vmcb *vmcb = &cpu_data->vmcb;
 651         vmcb->rip += inst_len;
 652 }
 653
 654 static void update_efer(struct per_cpu *cpu_data)
 655 {
 656         struct vmcb *vmcb = &cpu_data->vmcb;
 657         unsigned long efer = vmcb->efer;
 658
 659         if ((efer & (EFER_LME | EFER_LMA)) != EFER_LME)
 660                 return;
 661
 662         efer |= EFER_LMA;
 663
 664         /* Flush TLB on LMA/LME change: See APMv2, Sect. 15.16 */
 665         if ((vmcb->efer ^ efer) & EFER_LMA)
 666                 vcpu_tlb_flush();
 667
 668         vmcb->efer = efer;
 669         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 670 }
 671
 672 bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs)
 673 {
 674         struct per_cpu *cpu_data = this_cpu_data();
 675         struct vmcb *vmcb = &cpu_data->vmcb;
 676
 677         if (vmcb->efer & EFER_LMA) {
 678                 pg_structs->root_paging = x86_64_paging;
 679                 pg_structs->root_table_gphys =
 680                         vmcb->cr3 & 0x000ffffffffff000UL;
 681         } else if ((vmcb->cr0 & X86_CR0_PG) &&
 682                    !(vmcb->cr4 & X86_CR4_PAE)) {
 683                 pg_structs->root_paging = i386_paging;
 684                 pg_structs->root_table_gphys =
 685                         vmcb->cr3 & 0xfffff000UL;
 686         } else if (!(vmcb->cr0 & X86_CR0_PG)) {
 687                 /*
 688                  * Can be in non-paged protected mode as well, but
 689                  * the translation mechanism will stay the same ayway.
 690                  */
 691                 pg_structs->root_paging = realmode_paging;
 692                 /*
 693                  * This will make paging_get_guest_pages map the page
 694                  * that also contains the bootstrap code and, thus, is
 695                  * always present in a cell.
 696                  */
 697                 pg_structs->root_table_gphys = 0xff000;
 698         } else {
 699                 printk("FATAL: Unsupported paging mode\n");
 700                 return false;
 701         }
 702         return true;
 703 }
 704
 705 struct parse_context {
 706         unsigned int remaining;
 707         unsigned int size;
 708         unsigned long cs_base;
 709         const u8 *inst;
 710 };
 711
 712 static bool ctx_advance(struct parse_context *ctx,
 713                         unsigned long *pc,
 714                         struct guest_paging_structures *pg_structs)
 715 {
 716         if (!ctx->size) {
 717                 ctx->size = ctx->remaining;
 718                 ctx->inst = vcpu_map_inst(pg_structs, ctx->cs_base + *pc,
 719                                           &ctx->size);
 720                 if (!ctx->inst)
 721                         return false;
 722                 ctx->remaining -= ctx->size;
 723                 *pc += ctx->size;
 724         }
 725         return true;
 726 }
 727
 728 static bool x86_parse_mov_to_cr(struct per_cpu *cpu_data,
 729                                 unsigned long pc,
 730                                 unsigned char reg,
 731                                 unsigned long *gpr)
 732 {
 733         struct guest_paging_structures pg_structs;
 734         struct vmcb *vmcb = &cpu_data->vmcb;
 735         struct parse_context ctx = {};
 736         /* No prefixes are supported yet */
 737         u8 opcodes[] = {0x0f, 0x22}, modrm;
 738         bool ok = false;
 739         int n;
 740
 741         ctx.remaining = ARRAY_SIZE(opcodes);
 742         if (!vcpu_get_guest_paging_structs(&pg_structs))
 743                 goto out;
 744         ctx.cs_base = (vmcb->efer & EFER_LMA) ? 0 : vmcb->cs.base;
 745
 746         if (!ctx_advance(&ctx, &pc, &pg_structs))
 747                 goto out;
 748
 749         for (n = 0; n < ARRAY_SIZE(opcodes); n++, ctx.inst++) {
 750                 if (*(ctx.inst) != opcodes[n])
 751                         goto out;
 752                 if (!ctx_advance(&ctx, &pc, &pg_structs))
 753                         goto out;
 754         }
 755
 756         if (!ctx_advance(&ctx, &pc, &pg_structs))
 757                 goto out;
 758
 759         modrm = *(ctx.inst);
 760
 761         if (((modrm & 0x38) >> 3) != reg)
 762                 goto out;
 763
 764         if (gpr)
 765                 *gpr = (modrm & 0x7);
 766
 767         ok = true;
 768 out:
 769         return ok;
 770 }
 771
 772 /*
 773  * XXX: The only visible reason to have this function (vmx.c consistency
 774  * aside) is to prevent cells from setting invalid CD+NW combinations that
 775  * result in no more than VMEXIT_INVALID. Maybe we can get along without it
 776  * altogether?
 777  */
 778 static bool svm_handle_cr(struct registers *guest_regs,
 779                           struct per_cpu *cpu_data)
 780 {
 781         struct vmcb *vmcb = &cpu_data->vmcb;
 782         /* Workaround GCC 4.8 warning on uninitialized variable 'reg' */
 783         unsigned long reg = -1, val, bits;
 784         bool ok = true;
 785
 786         if (has_assists) {
 787                 if (!(vmcb->exitinfo1 & (1UL << 63))) {
 788                         panic_printk("FATAL: Unsupported CR access (LMSW or CLTS)\n");
 789                         ok = false;
 790                         goto out;
 791                 }
 792                 reg = vmcb->exitinfo1 & 0x07;
 793         } else {
 794                 if (!x86_parse_mov_to_cr(cpu_data, vmcb->rip, 0, &reg)) {
 795                         panic_printk("FATAL: Unable to parse MOV-to-CR instruction\n");
 796                         ok = false;
 797                         goto out;
 798                 }
 799         };
 800
 801         if (reg == 4)
 802                 val = vmcb->rsp;
 803         else
 804                 val = ((unsigned long *)guest_regs)[15 - reg];
 805
 806         vcpu_skip_emulated_instruction(X86_INST_LEN_MOV_TO_CR);
 807         /* Flush TLB on PG/WP/CD/NW change: See APMv2, Sect. 15.16 */
 808         bits = (X86_CR0_PG | X86_CR0_WP | X86_CR0_CD | X86_CR0_NW);
 809         if ((val ^ vmcb->cr0) & bits)
 810                 vcpu_tlb_flush();
 811         /* TODO: better check for #GP reasons */
 812         vmcb->cr0 = val & SVM_CR0_ALLOWED_BITS;
 813         if (val & X86_CR0_PG)
 814                 update_efer(cpu_data);
 815         vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 816
 817 out:
 818         return ok;
 819 }
 820
 821 static bool svm_handle_msr_read(struct registers *guest_regs,
 822                 struct per_cpu *cpu_data)
 823 {
 824         switch (guest_regs->rcx) {
 825         case MSR_IA32_PAT:
 826                 guest_regs->rax = cpu_data->vmcb.g_pat & 0xffffffff;
 827                 guest_regs->rdx = cpu_data->vmcb.g_pat >> 32;
 828                 break;
 829         default:
 830                 return vcpu_handle_msr_read(guest_regs);
 831         }
 832
 833         vcpu_skip_emulated_instruction(X86_INST_LEN_RDMSR);
 834         return true;
 835 }
 836
 837 static bool svm_handle_msr_write(struct registers *guest_regs,
 838                 struct per_cpu *cpu_data)
 839 {
 840         struct vmcb *vmcb = &cpu_data->vmcb;
 841         unsigned long efer, val;
 842
 843         switch (guest_regs->rcx) {
 844         case MSR_IA32_PAT:
 845                 vmcb->g_pat = (guest_regs->rax & 0xffffffff) |
 846                         (guest_regs->rdx << 32);
 847                 vmcb->clean_bits &= ~CLEAN_BITS_NP;
 848                 break;
 849         case MSR_EFER:
 850                 /* Never let a guest to disable SVME; see APMv2, Sect. 3.1.7 */
 851                 efer = (guest_regs->rax & 0xffffffff) |
 852                         (guest_regs->rdx << 32) | EFER_SVME;
 853                 /* Flush TLB on LME/NXE change: See APMv2, Sect. 15.16 */
 854                 if ((efer ^ vmcb->efer) & (EFER_LME | EFER_NXE))
 855                         vcpu_tlb_flush();
 856                 vmcb->efer = efer;
 857                 vmcb->clean_bits &= ~CLEAN_BITS_CRX;
 858                 break;
 859         case MTRR_DEFTYPE:
 860                 val = (guest_regs->rax & 0xffffffff) | (guest_regs->rdx << 32);
 861                 /*
 862                  * Quick (and very incomplete) guest MTRRs emulation.
 863                  *
 864                  * For Linux, emulating MTRR Enable bit seems to be enough.
 865                  * If it is cleared, we set hPAT to all zeroes, effectively
 866                  * making all NPT-mapped memory UC (see APMv2, Sect. 15.25.8).
 867                  *
 868                  * Otherwise, default PAT value is restored. This can also
 869                  * make NPT-mapped memory's type different from what Linux
 870                  * expects, however.
 871                  */
 872                 if (val & 0x800)
 873                         write_msr(MSR_IA32_PAT, PAT_RESET_VALUE);
 874                 else
 875                         write_msr(MSR_IA32_PAT, 0);
 876                 break;
 877         default:
 878                 return vcpu_handle_msr_write(guest_regs);
 879         }
 880
 881         vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
 882         return true;
 883 }
 884
 885 /*
 886  * TODO: This handles unaccelerated (non-AVIC) access. AVIC should
 887  * be treated separately in svm_handle_avic_access().
 888  */
 889 static bool svm_handle_apic_access(struct registers *guest_regs,
 890                                    struct per_cpu *cpu_data)
 891 {
 892         struct vmcb *vmcb = &cpu_data->vmcb;
 893         struct guest_paging_structures pg_structs;
 894         unsigned int inst_len, offset;
 895         bool is_write;
 896
 897         /* The caller is responsible for sanity checks */
 898         is_write = !!(vmcb->exitinfo1 & 0x2);
 899         offset = vmcb->exitinfo2 - XAPIC_BASE;
 900
 901         if (offset & 0x00f)
 902                 goto out_err;
 903
 904         if (!vcpu_get_guest_paging_structs(&pg_structs))
 905                 goto out_err;
 906
 907         inst_len = apic_mmio_access(guest_regs, cpu_data, vmcb->rip,
 908                                     &pg_structs, offset >> 4, is_write);
 909         if (!inst_len)
 910                 goto out_err;
 911
 912         vcpu_skip_emulated_instruction(inst_len);
 913         return true;
 914
 915 out_err:
 916         panic_printk("FATAL: Unhandled APIC access, offset %d, is_write: %d\n",
 917                      offset, is_write);
 918         return false;
 919 }
 920
 921 static void dump_guest_regs(struct registers *guest_regs, struct vmcb *vmcb)
 922 {
 923         panic_printk("RIP: %p RSP: %p FLAGS: %x\n", vmcb->rip,
 924                      vmcb->rsp, vmcb->rflags);
 925         panic_printk("RAX: %p RBX: %p RCX: %p\n", guest_regs->rax,
 926                      guest_regs->rbx, guest_regs->rcx);
 927         panic_printk("RDX: %p RSI: %p RDI: %p\n", guest_regs->rdx,
 928                      guest_regs->rsi, guest_regs->rdi);
 929         panic_printk("CS: %x BASE: %p AR-BYTES: %x EFER.LMA %d\n",
 930                      vmcb->cs.selector, vmcb->cs.base, vmcb->cs.access_rights,
 931                      !!(vmcb->efer & EFER_LMA));
 932         panic_printk("CR0: %p CR3: %p CR4: %p\n", vmcb->cr0,
 933                      vmcb->cr3, vmcb->cr4);
 934         panic_printk("EFER: %p\n", vmcb->efer);
 935 }
 936
 937 static void svm_get_vcpu_pf_intercept(struct per_cpu *cpu_data,
 938                                       struct vcpu_pf_intercept *out)
 939 {
 940         struct vmcb *vmcb = &cpu_data->vmcb;
 941
 942         out->phys_addr = vmcb->exitinfo2;
 943         out->is_write = !!(vmcb->exitinfo1 & 0x2);
 944 }
 945
 946 static void svm_get_vcpu_io_intercept(struct per_cpu *cpu_data,
 947                                       struct vcpu_io_intercept *out)
 948 {
 949         struct vmcb *vmcb = &cpu_data->vmcb;
 950         u64 exitinfo = vmcb->exitinfo1;
 951
 952         /* parse exit info for I/O instructions (see APM, 15.10.2 ) */
 953         out->port = (exitinfo >> 16) & 0xFFFF;
 954         out->size = (exitinfo >> 4) & 0x7;
 955         out->in = !!(exitinfo & 0x1);
 956         out->inst_len = vmcb->exitinfo2 - vmcb->rip;
 957         out->rep_or_str = !!(exitinfo & 0x0c);
 958 }
 959
 960 void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
 961 {
 962         struct vmcb *vmcb = &cpu_data->vmcb;
 963         struct vcpu_execution_state x_state;
 964         struct vcpu_pf_intercept pf;
 965         struct vcpu_io_intercept io;
 966         bool res = false;
 967         int sipi_vector;
 968
 969         /* Restore GS value expected by per_cpu data accessors */
 970         write_msr(MSR_GS_BASE, (unsigned long)cpu_data);
 971
 972         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
 973         /*
 974          * All guest state is marked unmodified; individual handlers must clear
 975          * the bits as needed.
 976          */
 977         vmcb->clean_bits = 0xffffffff;
 978
 979         switch (vmcb->exitcode) {
 980         case VMEXIT_INVALID:
 981                 panic_printk("FATAL: VM-Entry failure, error %d\n",
 982                              vmcb->exitcode);
 983                 break;
 984         case VMEXIT_NMI:
 985                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
 986                 /* Temporarily enable GIF to consume pending NMI */
 987                 asm volatile("stgi; clgi" : : : "memory");
 988                 sipi_vector = x86_handle_events(cpu_data);
 989                 if (sipi_vector >= 0) {
 990                         printk("CPU %d received SIPI, vector %x\n",
 991                                cpu_data->cpu_id, sipi_vector);
 992                         svm_vcpu_reset(cpu_data, sipi_vector);
 993                         memset(guest_regs, 0, sizeof(*guest_regs));
 994                 }
 995                 iommu_check_pending_faults(cpu_data);
 996                 return;
 997         case VMEXIT_CPUID:
 998                 /* FIXME: We are not intercepting CPUID now */
 999                 return;
1000         case VMEXIT_VMMCALL:
1001                 vcpu_vendor_get_execution_state(&x_state);
1002                 vcpu_handle_hypercall(guest_regs, &x_state);
1003                 return;
1004         case VMEXIT_CR0_SEL_WRITE:
1005                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_CR]++;
1006                 if (svm_handle_cr(guest_regs, cpu_data))
1007                         return;
1008                 break;
1009         case VMEXIT_MSR:
1010                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
1011                 if (!vmcb->exitinfo1)
1012                         res = svm_handle_msr_read(guest_regs, cpu_data);
1013                 else
1014                         res = svm_handle_msr_write(guest_regs, cpu_data);
1015                 if (res)
1016                         return;
1017                 break;
1018         case VMEXIT_NPF:
1019                 if ((vmcb->exitinfo1 & 0x7) == 0x7 &&
1020                      vmcb->exitinfo2 >= XAPIC_BASE &&
1021                      vmcb->exitinfo2 < XAPIC_BASE + PAGE_SIZE) {
1022                         /* APIC access in non-AVIC mode */
1023                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;
1024                         if (svm_handle_apic_access(guest_regs, cpu_data))
1025                                 return;
1026                 } else {
1027                         /* General MMIO (IOAPIC, PCI etc) */
1028                         cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
1029                         svm_get_vcpu_pf_intercept(cpu_data, &pf);
1030                         if (vcpu_handle_pt_violation(guest_regs, &pf))
1031                                 return;
1032                 }
1033
1034                 panic_printk("FATAL: Unhandled Nested Page Fault for (%p), "
1035                              "error code is %x\n", vmcb->exitinfo2,
1036                              vmcb->exitinfo1 & 0xf);
1037                 break;
1038         case VMEXIT_XSETBV:
1039                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XSETBV]++;
1040                 if ((guest_regs->rax & X86_XCR0_FP) &&
1041                     (guest_regs->rax & ~cpuid_eax(0x0d)) == 0 &&
1042                     guest_regs->rcx == 0 && guest_regs->rdx == 0) {
1043                         vcpu_skip_emulated_instruction(X86_INST_LEN_XSETBV);
1044                         asm volatile(
1045                                 "xsetbv"
1046                                 : /* no output */
1047                                 : "a" (guest_regs->rax), "c" (0), "d" (0));
1048                         return;
1049                 }
1050                 panic_printk("FATAL: Invalid xsetbv parameters: "
1051                              "xcr[%d] = %x:%x\n", guest_regs->rcx,
1052                              guest_regs->rdx, guest_regs->rax);
1053                 break;
1054         case VMEXIT_IOIO:
1055                 cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_PIO]++;
1056                 svm_get_vcpu_io_intercept(cpu_data, &io);
1057                 if (vcpu_handle_io_access(guest_regs, &io))
1058                         return;
1059                 break;
1060         /* TODO: Handle VMEXIT_AVIC_NOACCEL and VMEXIT_AVIC_INCOMPLETE_IPI */
1061         default:
1062                 panic_printk("FATAL: Unexpected #VMEXIT, exitcode %x, "
1063                              "exitinfo1 %p exitinfo2 %p\n",
1064                              vmcb->exitcode, vmcb->exitinfo1, vmcb->exitinfo2);
1065         }
1066         dump_guest_regs(guest_regs, vmcb);
1067         panic_park();
1068 }
1069
1070 void vcpu_park(struct per_cpu *cpu_data)
1071 {
1072         struct vmcb *vmcb = &cpu_data->vmcb;
1073
1074         svm_vcpu_reset(cpu_data, APIC_BSP_PSEUDO_SIPI);
1075         /* No need to clear VMCB Clean bit: vcpu_reset() already does this */
1076         vmcb->n_cr3 = paging_hvirt2phys(parked_mode_npt);
1077
1078         vcpu_tlb_flush();
1079 }
1080
1081 void vcpu_nmi_handler(void)
1082 {
1083 }
1084
1085 void vcpu_tlb_flush(void)
1086 {
1087         struct per_cpu *cpu_data = this_cpu_data();
1088         struct vmcb *vmcb = &cpu_data->vmcb;
1089
1090         if (has_flush_by_asid)
1091                 vmcb->tlb_control = SVM_TLB_FLUSH_GUEST;
1092         else
1093                 vmcb->tlb_control = SVM_TLB_FLUSH_ALL;
1094 }
1095
1096 const u8 *vcpu_get_inst_bytes(const struct guest_paging_structures *pg_structs,
1097                               unsigned long pc, unsigned int *size)
1098 {
1099         struct per_cpu *cpu_data = this_cpu_data();
1100         struct vmcb *vmcb = &cpu_data->vmcb;
1101         unsigned long start;
1102
1103         if (has_assists) {
1104                 if (!*size)
1105                         return NULL;
1106                 start = vmcb->rip - pc;
1107                 if (start < vmcb->bytes_fetched) {
1108                         *size = vmcb->bytes_fetched - start;
1109                         return &vmcb->guest_bytes[start];
1110                 } else {
1111                         return NULL;
1112                 }
1113         } else {
1114                 return vcpu_map_inst(pg_structs, pc, size);
1115         }
1116 }
1117
1118 void vcpu_vendor_get_cell_io_bitmap(struct cell *cell,
1119                                     struct vcpu_io_bitmap *iobm)
1120 {
1121         iobm->data = cell->svm.iopm;
1122         iobm->size = sizeof(cell->svm.iopm);
1123 }
1124
1125 void vcpu_vendor_get_execution_state(struct vcpu_execution_state *x_state)
1126 {
1127         struct per_cpu *cpu_data = this_cpu_data();
1128
1129         x_state->efer = cpu_data->vmcb.efer;
1130         x_state->rflags = cpu_data->vmcb.rflags;
1131         x_state->cs = cpu_data->vmcb.cs.selector;
1132         x_state->rip = cpu_data->vmcb.rip;
1133 }
1134
1135 /* GIF must be set for interrupts to be delivered (APMv2, Sect. 15.17) */
1136 void enable_irq(void)
1137 {
1138         asm volatile("stgi; sti" : : : "memory");
1139 }
1140
1141 /* Jailhouse runs with GIF cleared, so we need to restore this state */
1142 void disable_irq(void)
1143 {
1144         asm volatile("cli; clgi" : : : "memory");
1145 }