x86: Factor out vcpu_handle_msr_read/write

This will simplify the emulation of MTRR_DEF_TYPE. It already allows to
consolidate filtering for x2APIC MSRs and error reporting.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/x86/include/asm/vcpu.h b/hypervisor/arch/x86/include/asm/vcpu.h
index 8135248cecf5607935915bdf433d8d104c7e0a3d..2224d7c49f7f367233f51631b2caeadea5e5045d 100644 (file)
--- a/hypervisor/arch/x86/include/asm/vcpu.h
+++ b/hypervisor/arch/x86/include/asm/vcpu.h
@@ -111,4 +111,7 @@ bool vcpu_get_guest_paging_structs(struct guest_paging_structures *pg_structs);
 bool vcpu_handle_pt_violation(struct registers *guest_regs,
                              struct vcpu_pf_intercept *pf);
 
+bool vcpu_handle_msr_read(struct registers *guest_regs);
+bool vcpu_handle_msr_write(struct registers *guest_regs);
+
 #endif

diff --git a/hypervisor/arch/x86/svm.c b/hypervisor/arch/x86/svm.c
index 2275fe324bf9f1928f573f1aba76be395116caf8..691d0d0d23172083ccc6e0553cceb37f28788b7a 100644 (file)
--- a/hypervisor/arch/x86/svm.c
+++ b/hypervisor/arch/x86/svm.c
@@ -822,17 +822,12 @@ static bool svm_handle_msr_read(struct registers *guest_regs,
                struct per_cpu *cpu_data)
 {
        switch (guest_regs->rcx) {
-       case MSR_X2APIC_BASE ... MSR_X2APIC_END:
-               x2apic_handle_read(guest_regs);
-               break;
        case MSR_IA32_PAT:
                guest_regs->rax = cpu_data->vmcb.g_pat & 0xffffffff;
                guest_regs->rdx = cpu_data->vmcb.g_pat >> 32;
                break;
        default:
-               panic_printk("FATAL: Unhandled MSR read: %x\n",
-                            guest_regs->rcx);
-               return false;
+               return vcpu_handle_msr_read(guest_regs);
        }
 
        vcpu_skip_emulated_instruction(X86_INST_LEN_RDMSR);
@@ -846,10 +841,6 @@ static bool svm_handle_msr_write(struct registers *guest_regs,
        unsigned long efer, val;
 
        switch (guest_regs->rcx) {
-       case MSR_X2APIC_BASE ... MSR_X2APIC_END:
-               if (!x2apic_handle_write(guest_regs, cpu_data))
-                       return false;
-               break;
        case MSR_IA32_PAT:
                vmcb->g_pat = (guest_regs->rax & 0xffffffff) |
                        (guest_regs->rdx << 32);
@@ -884,9 +875,7 @@ static bool svm_handle_msr_write(struct registers *guest_regs,
                        write_msr(MSR_IA32_PAT, 0);
                break;
        default:
-               panic_printk("FATAL: Unhandled MSR write: %x\n",
-                            guest_regs->rcx);
-               return false;
+               return vcpu_handle_msr_write(guest_regs);
        }
 
        vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);

diff --git a/hypervisor/arch/x86/vcpu.c b/hypervisor/arch/x86/vcpu.c
index 97d8b4db0a9860cbf21bcf1fb91bb1d3a9f1fb1e..28279b0aa6e3267166c8cbc8cb57a1ac7ebab5ca 100644 (file)
--- a/hypervisor/arch/x86/vcpu.c
+++ b/hypervisor/arch/x86/vcpu.c
@@ -233,3 +233,36 @@ invalid_access:
                             pf->is_write ? "write" : "read", pf->phys_addr);
        return false;
 }
+
+bool vcpu_handle_msr_read(struct registers *guest_regs)
+{
+       switch (guest_regs->rcx) {
+       case MSR_X2APIC_BASE ... MSR_X2APIC_END:
+               x2apic_handle_read(guest_regs);
+               break;
+       default:
+               panic_printk("FATAL: Unhandled MSR read: %x\n",
+                            guest_regs->rcx);
+               return false;
+       }
+
+       vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
+       return true;
+}
+
+bool vcpu_handle_msr_write(struct registers *guest_regs)
+{
+       switch (guest_regs->rcx) {
+       case MSR_X2APIC_BASE ... MSR_X2APIC_END:
+               if (!x2apic_handle_write(guest_regs, this_cpu_data()))
+                       return false;
+               break;
+       default:
+               panic_printk("FATAL: Unhandled MSR write: %x\n",
+                            guest_regs->rcx);
+               return false;
+       }
+
+       vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
+       return true;
+}

diff --git a/hypervisor/arch/x86/vmx.c b/hypervisor/arch/x86/vmx.c
index 878bfc41041376df787ba6c456711b9c4cdaf6ca..f10372518532ece6df0f3739e01388ac4ddfb6f4 100644 (file)
--- a/hypervisor/arch/x86/vmx.c
+++ b/hypervisor/arch/x86/vmx.c
@@ -1073,30 +1073,17 @@ void vcpu_handle_exit(struct registers *guest_regs, struct per_cpu *cpu_data)
                break;
        case EXIT_REASON_MSR_READ:
                cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
-               if (guest_regs->rcx >= MSR_X2APIC_BASE &&
-                   guest_regs->rcx <= MSR_X2APIC_END) {
-                       vcpu_skip_emulated_instruction(X86_INST_LEN_RDMSR);
-                       x2apic_handle_read(guest_regs);
+               if (vcpu_handle_msr_read(guest_regs))
                        return;
-               }
-               panic_printk("FATAL: Unhandled MSR read: %08x\n",
-                            guest_regs->rcx);
                break;
        case EXIT_REASON_MSR_WRITE:
                cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MSR]++;
-               if (guest_regs->rcx >= MSR_X2APIC_BASE &&
-                   guest_regs->rcx <= MSR_X2APIC_END) {
-                       if (!x2apic_handle_write(guest_regs, cpu_data))
-                               break;
-                       vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
-                       return;
-               } else if (guest_regs->rcx == MSR_IA32_PERF_GLOBAL_CTRL) {
+               if (guest_regs->rcx == MSR_IA32_PERF_GLOBAL_CTRL) {
                        /* ignore writes */
                        vcpu_skip_emulated_instruction(X86_INST_LEN_WRMSR);
                        return;
-               }
-               panic_printk("FATAL: Unhandled MSR write: %08x\n",
-                            guest_regs->rcx);
+               } else if (vcpu_handle_msr_write(guest_regs))
+                       return;
                break;
        case EXIT_REASON_APIC_ACCESS:
                cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_XAPIC]++;