]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/tree - system/ip/can_merge/
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / ip / can_merge /
drwxr-xr-x   ..
-rw-r--r-- 697 can_merge.vhd
-rw-r--r-- 8497 component.xml
drwxr-xr-x - xgui