--- /dev/null
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>user.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>can_crossbar</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wstrb</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_wready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIZ_NUM_REG</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI_RST</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S00_AXI_CLK</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s00_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
+ <spirit:name>S00_AXI</spirit:name>
+ <spirit:addressBlock>
+ <spirit:name>S00_AXI_reg</spirit:name>
+ <spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
+ <spirit:range spirit:format="long">4096</spirit:range>
+ <spirit:width spirit:format="long">32</spirit:width>
+ <spirit:usage>register</spirit:usage>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>OFFSET_BASE_PARAM</spirit:name>
+ <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OFFSET_HIGH_PARAM</spirit:name>
+ <spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI.S00_AXI_REG.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:addressBlock>
+ </spirit:memoryMap>
+ </spirit:memoryMaps>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>can_crossbar_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>73ee1312</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>can_crossbar_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>73ee1312</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_softwaredriver</spirit:name>
+ <spirit:displayName>Software Driver</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>f1bf0c25</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>fd592ead</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>bd_tcl</spirit:name>
+ <spirit:displayName>Block Diagram</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>bd_tcl_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>45a2f450</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>can1_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can2_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can3_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can4_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can1_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can2_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can3_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can4_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc1_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc2_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc3_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc4_tx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc1_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc2_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc3_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ifc4_rx</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>can_stby</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_awaddr</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_awprot</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_awvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_awready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_wdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_wstrb</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_wvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_wready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_bresp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_bvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_bready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_araddr</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_arprot</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_arvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_arready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_rdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_rresp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_rvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_rready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_aclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>s00_axi_aresetn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+ <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI data bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI address bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_6fc15197</spirit:name>
+ <spirit:enumeration>32</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_ce1226b1</spirit:name>
+ <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+ <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/can_crossbar_v1_0_S00_AXI.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_crossbar_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_4e4d777f</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/can_crossbar_v1_0_S00_AXI.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/can_crossbar_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>drivers/can_crossbar_v1_0/data/can_crossbar.mdd</spirit:name>
+ <spirit:userFileType>mdd</spirit:userFileType>
+ <spirit:userFileType>driver_mdd</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/can_crossbar_v1_0/data/can_crossbar.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>driver_tcl</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/can_crossbar_v1_0/src/Makefile</spirit:name>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/can_crossbar_v1_0/src/can_crossbar.h</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/can_crossbar_v1_0/src/can_crossbar.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/can_crossbar_v1_0/src/can_crossbar_selftest.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>xgui/can_crossbar_v1_0.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_fd592ead</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>bd_tcl_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>bd/bd.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>CAN Crossbar</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI data bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXI address bus</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">4</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
+ <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
+ <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">can_crossbar_v1_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>can_crossbar_v1.0</xilinx:displayName>
+ <xilinx:coreRevision>3</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2016-05-12T00:55:21Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="user.org:user:can_crossbar:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/bakalarka/canbench-sw/system/ip/can_crossbar_1.0</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2016.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="d9a0b4b8"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="493665f4"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="37646b60"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="94557fa6"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4429bb0c"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="7691242a"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
--- /dev/null
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER can_crossbar
+ OPTION supported_peripherals = (can_crossbar);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = can_crossbar;
+END DRIVER
--- /dev/null
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "can_crossbar" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}
--- /dev/null
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling can_crossbar..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
--- /dev/null
+
+
+/***************************** Include Files *******************************/
+#include "can_crossbar.h"
+
+/************************** Function Definitions ***************************/
--- /dev/null
+
+#ifndef CAN_CROSSBAR_H
+#define CAN_CROSSBAR_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define CAN_CROSSBAR_S00_AXI_SLV_REG0_OFFSET 0
+#define CAN_CROSSBAR_S00_AXI_SLV_REG1_OFFSET 4
+#define CAN_CROSSBAR_S00_AXI_SLV_REG2_OFFSET 8
+#define CAN_CROSSBAR_S00_AXI_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a CAN_CROSSBAR register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the CAN_CROSSBARdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void CAN_CROSSBAR_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define CAN_CROSSBAR_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a CAN_CROSSBAR register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the CAN_CROSSBAR device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 CAN_CROSSBAR_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define CAN_CROSSBAR_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the CAN_CROSSBAR instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus CAN_CROSSBAR_Reg_SelfTest(void * baseaddr_p);
+
+#endif // CAN_CROSSBAR_H
--- /dev/null
+
+/***************************** Include Files *******************************/
+#include "can_crossbar.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the CAN_CROSSBARinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus CAN_CROSSBAR_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ CAN_CROSSBAR_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( CAN_CROSSBAR_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
--- /dev/null
+
+`timescale 1 ns / 1 ps
+
+`include "can_crossbar_v1_0_tb_include.vh"
+
+// lite_response Type Defines
+`define RESPONSE_OKAY 2'b00
+`define RESPONSE_EXOKAY 2'b01
+`define RESP_BUS_WIDTH 2
+`define BURST_TYPE_INCR 2'b01
+`define BURST_TYPE_WRAP 2'b10
+
+// AMBA AXI4 Lite Range Constants
+`define S00_AXI_MAX_BURST_LENGTH 1
+`define S00_AXI_DATA_BUS_WIDTH 32
+`define S00_AXI_ADDRESS_BUS_WIDTH 32
+`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
+
+module can_crossbar_v1_0_tb;
+ reg tb_ACLK;
+ reg tb_ARESETn;
+
+ // Create an instance of the example tb
+ `BD_WRAPPER dut (.ACLK(tb_ACLK),
+ .ARESETN(tb_ARESETn));
+
+ // Local Variables
+
+ // AMBA S00_AXI AXI4 Lite Local Reg
+ reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
+ reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
+ reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
+ reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
+ reg [3-1:0] S00_AXI_mtestProtection_lite;
+ integer S00_AXI_mtestvectorlite; // Master side testvector
+ integer S00_AXI_mtestdatasizelite;
+ integer result_slave_lite;
+
+
+ // Simple Reset Generator and test
+ initial begin
+ tb_ARESETn = 1'b0;
+ #500;
+ // Release the reset on the posedge of the clk.
+ @(posedge tb_ACLK);
+ tb_ARESETn = 1'b1;
+ @(posedge tb_ACLK);
+ end
+
+ // Simple Clock Generator
+ initial tb_ACLK = 1'b0;
+ always #10 tb_ACLK = !tb_ACLK;
+
+ //------------------------------------------------------------------------
+ // TEST LEVEL API: CHECK_RESPONSE_OKAY
+ //------------------------------------------------------------------------
+ // Description:
+ // CHECK_RESPONSE_OKAY(lite_response)
+ // This task checks if the return lite_response is equal to OKAY
+ //------------------------------------------------------------------------
+ task automatic CHECK_RESPONSE_OKAY;
+ input [`RESP_BUS_WIDTH-1:0] response;
+ begin
+ if (response !== `RESPONSE_OKAY) begin
+ $display("TESTBENCH ERROR! lite_response is not OKAY",
+ "\n expected = 0x%h",`RESPONSE_OKAY,
+ "\n actual = 0x%h",response);
+ $stop;
+ end
+ end
+ endtask
+
+ //------------------------------------------------------------------------
+ // TEST LEVEL API: COMPARE_LITE_DATA
+ //------------------------------------------------------------------------
+ // Description:
+ // COMPARE_LITE_DATA(expected,actual)
+ // This task checks if the actual data is equal to the expected data.
+ // X is used as don't care but it is not permitted for the full vector
+ // to be don't care.
+ //------------------------------------------------------------------------
+ `define S_AXI_DATA_BUS_WIDTH 32
+ task automatic COMPARE_LITE_DATA;
+ input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
+ input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
+ begin
+ if (expected === 'hx || actual === 'hx) begin
+ $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
+ result_slave_lite = 0;
+ $stop;
+ end
+
+ if (actual != expected) begin
+ $display("TESTBENCH ERROR! Data expected is not equal to actual.",
+ "\nexpected = 0x%h",expected,
+ "\nactual = 0x%h",actual);
+ result_slave_lite = 0;
+ $stop;
+ end
+ else
+ begin
+ $display("TESTBENCH Passed! Data expected is equal to actual.",
+ "\n expected = 0x%h",expected,
+ "\n actual = 0x%h",actual);
+ end
+ end
+ endtask
+
+ task automatic S00_AXI_TEST;
+ begin
+ $display("---------------------------------------------------------");
+ $display("EXAMPLE TEST : S00_AXI");
+ $display("Simple register write and read example");
+ $display("---------------------------------------------------------");
+
+ S00_AXI_mtestvectorlite = 0;
+ S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
+ S00_AXI_mtestProtection_lite = 0;
+ S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
+
+ result_slave_lite = 1;
+
+ for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
+ begin
+ dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
+ S00_AXI_mtestProtection_lite,
+ S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
+ S00_AXI_mtestdatasizelite,
+ S00_AXI_lite_response);
+ $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
+ CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
+ dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
+ S00_AXI_mtestProtection_lite,
+ S00_AXI_rd_data_lite,
+ S00_AXI_lite_response);
+ $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
+ CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
+ COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
+ $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
+ S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
+ end
+
+ $display("---------------------------------------------------------");
+ $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
+ if ( result_slave_lite ) begin
+ $display("PTGEN_TEST: PASSED!");
+ end else begin
+ $display("PTGEN_TEST: FAILED!");
+ end
+ $display("---------------------------------------------------------");
+ end
+ endtask
+
+ // Create the test vectors
+ initial begin
+ // When performing debug enable all levels of INFO messages.
+ wait(tb_ARESETn === 0) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+
+ dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
+
+ // Create test data vectors
+ S00_AXI_test_data_lite[0] = 32'h0101FFFF;
+ S00_AXI_test_data_lite[1] = 32'habcd0001;
+ S00_AXI_test_data_lite[2] = 32'hdead0011;
+ S00_AXI_test_data_lite[3] = 32'hbeef0011;
+ end
+
+ // Drive the BFM
+ initial begin
+ // Wait for end of reset
+ wait(tb_ARESETn === 0) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+ wait(tb_ARESETn === 1) @(posedge tb_ACLK);
+
+ S00_AXI_TEST();
+
+ end
+
+endmodule
--- /dev/null
+proc create_ipi_design { offsetfile design_name } {
+ create_bd_design $design_name
+ open_bd_design $design_name
+
+ # Create Clock and Reset Ports
+ set ACLK [ create_bd_port -dir I -type clk ACLK ]
+ set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
+ set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
+ set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
+ set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
+
+ # Create instance: can_crossbar_0, and set properties
+ set can_crossbar_0 [ create_bd_cell -type ip -vlnv user.org:user:can_crossbar:1.0 can_crossbar_0]
+
+ # Create instance: master_0, and set properties
+ set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0]
+ set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0
+
+ # Create interface connections
+ connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins can_crossbar_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins can_crossbar_0/S00_AXI_ACLK]
+ connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins can_crossbar_0/S00_AXI_ARESETN]
+
+ # Auto assign address
+ assign_bd_address
+
+ # Copy all address to interface_address.vh file
+ set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
+ upvar 1 $offsetfile offset_file
+ set offset_file "${bd_path}/can_crossbar_v1_0_tb_include.vh"
+ set fp [open $offset_file "w"]
+ puts $fp "`ifndef can_crossbar_v1_0_tb_include_vh_"
+ puts $fp "`define can_crossbar_v1_0_tb_include_vh_\n"
+ puts $fp "//Configuration current bd names"
+ puts $fp "`define BD_INST_NAME ${design_name}_i"
+ puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
+ puts $fp "//Configuration address parameters"
+
+ set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]]
+ set offset_hex [string replace $offset 0 1 "32'h"]
+ puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}"
+
+ puts $fp "`endif"
+ close $fp
+}
+
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:can_crossbar:1.0]]]]
+set test_bench_file ${ip_path}/example_designs/bfm_design/can_crossbar_v1_0_tb.v
+set interface_address_vh_file ""
+
+# Set IP Repository and Update IP Catalogue
+set repo_paths [get_property ip_repo_paths [current_fileset]]
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+ set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+ update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+ set design_name "can_crossbar_v1_0_bfm_${i}"
+ if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+ break
+ }
+}
+
+create_ipi_design interface_address_vh_file ${design_name}
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+set_property SOURCE_SET sources_1 [get_filesets sim_1]
+import_files -fileset sim_1 -norecurse -force $test_bench_file
+remove_files -quiet -fileset sim_1 can_crossbar_v1_0_tb_include.vh
+import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
+set_property top can_crossbar_v1_0_tb [get_filesets sim_1]
+set_property top_lib {} [get_filesets sim_1]
+set_property top_file {} [get_filesets sim_1]
+launch_xsim -simset sim_1 -mode behavioral
+restart
+run 1000 us
--- /dev/null
+# Runtime Tcl commands to interact with - can_crossbar_v1_0
+
+# Sourcing design address info tcl
+set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+source ${bd_path}/can_crossbar_v1_0_include.tcl
+
+# jtag axi master interface hardware name, change as per your design.
+set jtag_axi_master hw_axi_1
+set ec 0
+
+# hw test script
+# Delete all previous axis transactions
+if { [llength [get_hw_axi_txns -quiet]] } {
+ delete_hw_axi_txn [get_hw_axi_txns -quiet]
+}
+
+
+# Test all lite slaves.
+set wdata_1 abcd1234
+
+# Test: S00_AXI
+# Create a write transaction at s00_axi_addr address
+create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
+# Create a read transaction at s00_axi_addr address
+create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
+# Initiate transactions
+run_hw_axi r_s00_axi_addr
+run_hw_axi w_s00_axi_addr
+run_hw_axi r_s00_axi_addr
+set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
+# Compare read data
+if { $rdata_tmp == $wdata_1 } {
+ puts "Data comparison test pass for - S00_AXI"
+} else {
+ puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
+ inc ec
+}
+
+# Check error flag
+if { $ec == 0 } {
+ puts "PTGEN_TEST: PASSED!"
+} else {
+ puts "PTGEN_TEST: FAILED!"
+}
+
--- /dev/null
+
+proc create_ipi_design { offsetfile design_name } {
+
+ create_bd_design $design_name
+ open_bd_design $design_name
+
+ # Create and configure Clock/Reset
+ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
+ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
+
+ #check if current_board is set, if true - figure out required clocks.
+ set is_board_clock_found 0
+ set is_board_reset_found 0
+ set external_reset_port ""
+ set external_clock_port ""
+
+ if { [current_board_part -quiet] != "" } {
+
+ #check if any reset interface exists in board.
+ set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ]
+ if { $board_reset ne "" } {
+ set is_board_reset_found 1
+ apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design]
+ apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design]
+ set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]]
+ if { $external_rst ne "" } {
+ set external_reset_port [get_property NAME $external_rst]
+ }
+ } else {
+ send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually."
+ }
+
+ # check for differential clock, exclude any special clocks which has TYPE property.
+ set board_clock_busifs ""
+ foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] {
+ set type [get_property PARAM.TYPE $busif]
+ if { $type == "" } {
+ set board_clock_busifs $busif
+ break
+ }
+ }
+ if { $board_clock_busifs ne "" } {
+ apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design]
+ set is_board_clock_found 1
+ } else {
+ # check for single ended clock
+ set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ]
+ if { $board_sclock_busifs ne "" } {
+ apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design]
+ set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]]
+ if { $external_clk ne "" } {
+ set external_clock_port [get_property NAME $external_clk]
+ }
+ set is_board_clock_found 1
+ } else {
+ send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually."
+ }
+ }
+
+ } else {
+ send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually."
+ }
+
+ #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning.
+ if { $is_board_reset_found == 0 } {
+ create_bd_port -dir I -type rst reset_rtl
+ set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
+ connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
+ connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
+ set external_reset_port reset_rtl
+ }
+ if { $is_board_clock_found == 0 } {
+ create_bd_port -dir I -type clk clock_rtl
+ connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
+ set external_clock_port clock_rtl
+ }
+
+ #Avoid IPI DRC, make clock port synchronous to reset
+ if { $external_clock_port ne "" && $external_reset_port ne "" } {
+ set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
+ }
+
+ # Connect other sys_reset pins
+ connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
+
+ # Create instance: can_crossbar_0, and set properties
+ set can_crossbar_0 [ create_bd_cell -type ip -vlnv user.org:user:can_crossbar:1.0 can_crossbar_0 ]
+
+ # Create instance: jtag_axi_0, and set properties
+ set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
+ set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
+ connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Create instance: axi_peri_interconnect, and set properties
+ set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
+ set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
+ connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+ connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
+
+ set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+ # Connect all clock & reset of can_crossbar_0 slave interfaces..
+ connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins can_crossbar_0/S00_AXI]
+ connect_bd_net [get_bd_pins can_crossbar_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
+ connect_bd_net [get_bd_pins can_crossbar_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
+
+
+ # Auto assign address
+ assign_bd_address
+
+ # Copy all address to can_crossbar_v1_0_include.tcl file
+ set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
+ upvar 1 $offsetfile offset_file
+ set offset_file "${bd_path}/can_crossbar_v1_0_include.tcl"
+ set fp [open $offset_file "w"]
+ puts $fp "# Configuration address parameters"
+
+ set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_can_crossbar_0_S00_AXI_* ]]
+ puts $fp "set s00_axi_addr ${offset}"
+
+ close $fp
+}
+
+# Set IP Repository and Update IP Catalogue
+set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores user.org:user:can_crossbar:1.0]]]]
+set hw_test_file ${ip_path}/example_designs/debug_hw_design/can_crossbar_v1_0_hw_test.tcl
+
+set repo_paths [get_property ip_repo_paths [current_fileset]]
+if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
+ set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
+ update_ip_catalog
+}
+
+set design_name ""
+set all_bd {}
+set all_bd_files [get_files *.bd -quiet]
+foreach file $all_bd_files {
+set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
+set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
+lappend all_bd $bd_name
+}
+
+for { set i 1 } { 1 } { incr i } {
+ set design_name "can_crossbar_v1_0_hw_${i}"
+ if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
+ break
+ }
+}
+
+set intf_address_include_file ""
+create_ipi_design intf_address_include_file ${design_name}
+save_bd_design
+validate_bd_design
+
+set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
+import_files -force -norecurse $wrapper_file
+
+puts "-------------------------------------------------------------------------------------------------"
+puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
+puts " please perform following steps to test design in targeted board."
+puts "1. Generate bitstream"
+puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
+puts "3. Download generated bitstream"
+puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
+puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
+puts " : source -notrace ${hw_test_file}"
+puts "-------------------------------------------------------------------------------------------------"
+
--- /dev/null
+
+`timescale 1 ns / 1 ps
+
+ module can_crossbar_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Slave Bus Interface S00_AXI
+ parameter integer C_S00_AXI_DATA_WIDTH = 32,
+ parameter integer C_S00_AXI_ADDR_WIDTH = 4
+ )
+ (
+ // Users to add ports here
+ input wire can1_rx,
+ input wire can2_rx,
+ input wire can3_rx,
+ input wire can4_rx,
+
+ output wire can1_tx,
+ output wire can2_tx,
+ output wire can3_tx,
+ output wire can4_tx,
+
+ input wire ifc1_tx,
+ input wire ifc2_tx,
+ input wire ifc3_tx,
+ input wire ifc4_tx,
+
+ output wire ifc1_rx,
+ output wire ifc2_rx,
+ output wire ifc3_rx,
+ output wire ifc4_rx,
+
+ output wire can_stby,
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Slave Bus Interface S00_AXI
+ input wire s00_axi_aclk,
+ input wire s00_axi_aresetn,
+ input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
+ input wire [2 : 0] s00_axi_awprot,
+ input wire s00_axi_awvalid,
+ output wire s00_axi_awready,
+ input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
+ input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
+ input wire s00_axi_wvalid,
+ output wire s00_axi_wready,
+ output wire [1 : 0] s00_axi_bresp,
+ output wire s00_axi_bvalid,
+ input wire s00_axi_bready,
+ input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
+ input wire [2 : 0] s00_axi_arprot,
+ input wire s00_axi_arvalid,
+ output wire s00_axi_arready,
+ output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
+ output wire [1 : 0] s00_axi_rresp,
+ output wire s00_axi_rvalid,
+ input wire s00_axi_rready
+ );
+// Instantiation of Axi Bus Interface S00_AXI
+ can_crossbar_v1_0_S00_AXI # (
+ .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
+ .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
+ ) can_crossbar_v1_0_S00_AXI_inst (
+ .can_rx({can4_rx, can3_rx, can2_rx, can1_rx}),
+ .can_tx({can4_tx, can3_tx, can2_tx, can1_tx}),
+ .ifc_rx({ifc4_rx, ifc3_rx, ifc2_rx, ifc1_rx}),
+ .ifc_tx({ifc4_tx, ifc3_tx, ifc2_tx, ifc1_tx}),
+ .can_stby(can_stby),
+ .S_AXI_ACLK(s00_axi_aclk),
+ .S_AXI_ARESETN(s00_axi_aresetn),
+ .S_AXI_AWADDR(s00_axi_awaddr),
+ .S_AXI_AWPROT(s00_axi_awprot),
+ .S_AXI_AWVALID(s00_axi_awvalid),
+ .S_AXI_AWREADY(s00_axi_awready),
+ .S_AXI_WDATA(s00_axi_wdata),
+ .S_AXI_WSTRB(s00_axi_wstrb),
+ .S_AXI_WVALID(s00_axi_wvalid),
+ .S_AXI_WREADY(s00_axi_wready),
+ .S_AXI_BRESP(s00_axi_bresp),
+ .S_AXI_BVALID(s00_axi_bvalid),
+ .S_AXI_BREADY(s00_axi_bready),
+ .S_AXI_ARADDR(s00_axi_araddr),
+ .S_AXI_ARPROT(s00_axi_arprot),
+ .S_AXI_ARVALID(s00_axi_arvalid),
+ .S_AXI_ARREADY(s00_axi_arready),
+ .S_AXI_RDATA(s00_axi_rdata),
+ .S_AXI_RRESP(s00_axi_rresp),
+ .S_AXI_RVALID(s00_axi_rvalid),
+ .S_AXI_RREADY(s00_axi_rready)
+ );
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
--- /dev/null
+
+`timescale 1 ns / 1 ps
+
+module cross_impl #()
+(
+ input wire [3:0] can_rx,
+ output wire [3:0] can_tx,
+ input wire [3:0] ifc_tx,
+ output wire [3:0] ifc_rx,
+ output wire can_stby,
+
+ input wire [31:0] ctrl_word
+);
+wire [1:0] can1_line;
+wire [1:0] can2_line;
+wire [1:0] can3_line;
+wire [1:0] can4_line;
+wire [1:0] ifc1_line;
+wire [1:0] ifc2_line;
+wire [1:0] ifc3_line;
+wire [1:0] ifc4_line;
+wire [3:0] can_en;
+
+assign {can4_line, can3_line, can2_line, can1_line} = ctrl_word[7:0];
+assign {ifc4_line, ifc3_line, ifc2_line, ifc1_line} = ctrl_word[15:8];
+assign can_en = ctrl_word[20:16];
+assign can_stby = ctrl_word[21];
+
+wire [3:0] line_rx;
+wire [3:0] line_tx;
+
+/*
+assign ifc_rx[0] = (ifc1_line == 0 ? line_rx[0] : 1'b1)
+ & (ifc1_line == 1 ? line_rx[1] : 1'b1)
+ & (ifc1_line == 2 ? line_rx[2] : 1'b1)
+ & (ifc1_line == 3 ? line_rx[3] : 1'b1);
+assign ifc_rx[1] = (ifc2_line == 0 ? line_rx[0] : 1'b1)
+ & (ifc2_line == 1 ? line_rx[1] : 1'b1)
+ & (ifc2_line == 2 ? line_rx[2] : 1'b1)
+ & (ifc2_line == 3 ? line_rx[3] : 1'b1);
+assign ifc_rx[2] = (ifc3_line == 0 ? line_rx[0] : 1'b1)
+ & (ifc3_line == 1 ? line_rx[1] : 1'b1)
+ & (ifc3_line == 2 ? line_rx[2] : 1'b1)
+ & (ifc3_line == 3 ? line_rx[3] : 1'b1);
+assign ifc_rx[3] = (ifc4_line == 0 ? line_rx[0] : 1'b1)
+ & (ifc4_line == 1 ? line_rx[1] : 1'b1)
+ & (ifc4_line == 2 ? line_rx[2] : 1'b1)
+ & (ifc4_line == 3 ? line_rx[3] : 1'b1);
+*/
+assign ifc_rx[0] = line_rx[ifc1_line];
+assign ifc_rx[1] = line_rx[ifc2_line];
+assign ifc_rx[2] = line_rx[ifc3_line];
+assign ifc_rx[3] = line_rx[ifc4_line];
+
+assign line_rx[0] = ~can_en[0] ? 1'b1 :
+ (can1_line == 0 ? can_rx[0] : 1'b1)
+ & (can1_line == 1 ? can_rx[1] : 1'b1)
+ & (can1_line == 2 ? can_rx[2] : 1'b1)
+ & (can1_line == 3 ? can_rx[3] : 1'b1);
+assign line_rx[1] = ~can_en[1] ? 1'b1 :
+ (can2_line == 0 ? can_rx[0] : 1'b1)
+ & (can2_line == 1 ? can_rx[1] : 1'b1)
+ & (can2_line == 2 ? can_rx[2] : 1'b1)
+ & (can2_line == 3 ? can_rx[3] : 1'b1);
+assign line_rx[2] = ~can_en[2] ? 1'b1 :
+ (can3_line == 0 ? can_rx[0] : 1'b1)
+ & (can3_line == 1 ? can_rx[1] : 1'b1)
+ & (can3_line == 2 ? can_rx[2] : 1'b1)
+ & (can3_line == 3 ? can_rx[3] : 1'b1);
+assign line_rx[3] = ~can_en[3] ? 1'b1 :
+ (can4_line == 0 ? can_rx[0] : 1'b1)
+ & (can4_line == 1 ? can_rx[1] : 1'b1)
+ & (can4_line == 2 ? can_rx[2] : 1'b1)
+ & (can4_line == 3 ? can_rx[3] : 1'b1);
+
+/*
+assign can_tx[0] = ~can_en[0] ? 1'b1 :
+ (can1_line == 0 ? line_tx[0] : 1'b1)
+ & (can1_line == 1 ? line_tx[1] : 1'b1)
+ & (can1_line == 2 ? line_tx[2] : 1'b1)
+ & (can1_line == 3 ? line_tx[3] : 1'b1);
+assign can_tx[1] = ~can_en[1] ? 1'b1 :
+ (can2_line == 0 ? line_tx[0] : 1'b1)
+ & (can2_line == 1 ? line_tx[1] : 1'b1)
+ & (can2_line == 2 ? line_tx[2] : 1'b1)
+ & (can2_line == 3 ? line_tx[3] : 1'b1);
+assign can_tx[2] = ~can_en[2] ? 1'b1 :
+ (can3_line == 0 ? line_tx[0] : 1'b1)
+ & (can3_line == 1 ? line_tx[1] : 1'b1)
+ & (can3_line == 2 ? line_tx[2] : 1'b1)
+ & (can3_line == 3 ? line_tx[3] : 1'b1);
+assign can_tx[3] = ~can_en[3] ? 1'b1 :
+ (can4_line == 0 ? line_tx[0] : 1'b1)
+ & (can4_line == 1 ? line_tx[1] : 1'b1)
+ & (can4_line == 2 ? line_tx[2] : 1'b1)
+ & (can4_line == 3 ? line_tx[3] : 1'b1);
+*/
+assign can_tx[0] = can_en[0] ? line_tx[can1_line] : 1'b1;
+assign can_tx[1] = can_en[1] ? line_tx[can2_line] : 1'b1;
+assign can_tx[2] = can_en[2] ? line_tx[can3_line] : 1'b1;
+assign can_tx[3] = can_en[3] ? line_tx[can4_line] : 1'b1;
+
+assign line_tx[0] = (ifc1_line == 0 ? ifc_tx[0] : 1'b1)
+ & (ifc1_line == 1 ? ifc_tx[1] : 1'b1)
+ & (ifc1_line == 2 ? ifc_tx[2] : 1'b1)
+ & (ifc1_line == 3 ? ifc_tx[3] : 1'b1);
+assign line_tx[1] = (ifc2_line == 0 ? ifc_tx[0] : 1'b1)
+ & (ifc2_line == 1 ? ifc_tx[1] : 1'b1)
+ & (ifc2_line == 2 ? ifc_tx[2] : 1'b1)
+ & (ifc2_line == 3 ? ifc_tx[3] : 1'b1);
+assign line_tx[2] = (ifc3_line == 0 ? ifc_tx[0] : 1'b1)
+ & (ifc3_line == 1 ? ifc_tx[1] : 1'b1)
+ & (ifc3_line == 2 ? ifc_tx[2] : 1'b1)
+ & (ifc3_line == 3 ? ifc_tx[3] : 1'b1);
+assign line_tx[3] = (ifc4_line == 0 ? ifc_tx[0] : 1'b1)
+ & (ifc4_line == 1 ? ifc_tx[1] : 1'b1)
+ & (ifc4_line == 2 ? ifc_tx[2] : 1'b1)
+ & (ifc4_line == 3 ? ifc_tx[3] : 1'b1);
+
+endmodule
+
+ module can_crossbar_v1_0_S00_AXI #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXI data bus
+ parameter integer C_S_AXI_DATA_WIDTH = 32,
+ // Width of S_AXI address bus
+ parameter integer C_S_AXI_ADDR_WIDTH = 4
+ )
+ (
+ // Users to add ports here
+ input wire [3:0] can_rx,
+ output wire [3:0] can_tx,
+ input wire [3:0] ifc_tx,
+ output wire [3:0] ifc_rx,
+ output wire can_stby,
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global Clock Signal
+ input wire S_AXI_ACLK,
+ // Global Reset Signal. This Signal is Active LOW
+ input wire S_AXI_ARESETN,
+ // Write address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+ // Write channel Protection type. This signal indicates the
+ // privilege and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_AWPROT,
+ // Write address valid. This signal indicates that the master signaling
+ // valid write address and control information.
+ input wire S_AXI_AWVALID,
+ // Write address ready. This signal indicates that the slave is ready
+ // to accept an address and associated control signals.
+ output wire S_AXI_AWREADY,
+ // Write data (issued by master, acceped by Slave)
+ input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+ // Write strobes. This signal indicates which byte lanes hold
+ // valid data. There is one write strobe bit for each eight
+ // bits of the write data bus.
+ input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available.
+ input wire S_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ output wire S_AXI_WREADY,
+ // Write response. This signal indicates the status
+ // of the write transaction.
+ output wire [1 : 0] S_AXI_BRESP,
+ // Write response valid. This signal indicates that the channel
+ // is signaling a valid write response.
+ output wire S_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ input wire S_AXI_BREADY,
+ // Read address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether the
+ // transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_ARPROT,
+ // Read address valid. This signal indicates that the channel
+ // is signaling valid read address and control information.
+ input wire S_AXI_ARVALID,
+ // Read address ready. This signal indicates that the slave is
+ // ready to accept an address and associated control signals.
+ output wire S_AXI_ARREADY,
+ // Read data (issued by slave)
+ output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+ // Read response. This signal indicates the status of the
+ // read transfer.
+ output wire [1 : 0] S_AXI_RRESP,
+ // Read valid. This signal indicates that the channel is
+ // signaling the required read data.
+ output wire S_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ input wire S_AXI_RREADY
+ );
+
+ // AXI4LITE signals
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awready;
+ reg axi_wready;
+ reg [1 : 0] axi_bresp;
+ reg axi_bvalid;
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arready;
+ reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
+ reg [1 : 0] axi_rresp;
+ reg axi_rvalid;
+
+ // Example-specific design signals
+ // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ // ADDR_LSB is used for addressing 32/64 bit registers/memories
+ // ADDR_LSB = 2 for 32 bits (n downto 2)
+ // ADDR_LSB = 3 for 64 bits (n downto 3)
+ localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+ localparam integer OPT_MEM_ADDR_BITS = 1;
+ //----------------------------------------------
+ //-- Signals for user logic register space example
+ //------------------------------------------------
+ //-- Number of Slave Registers 4
+ reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
+ reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
+ reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
+ reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
+ wire slv_reg_rden;
+ wire slv_reg_wren;
+ reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
+ integer byte_index;
+
+ // I/O Connections assignments
+
+ assign S_AXI_AWREADY = axi_awready;
+ assign S_AXI_WREADY = axi_wready;
+ assign S_AXI_BRESP = axi_bresp;
+ assign S_AXI_BVALID = axi_bvalid;
+ assign S_AXI_ARREADY = axi_arready;
+ assign S_AXI_RDATA = axi_rdata;
+ assign S_AXI_RRESP = axi_rresp;
+ assign S_AXI_RVALID = axi_rvalid;
+ // Implement axi_awready generation
+ // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awready <= 1'b0;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
+ begin
+ // slave is ready to accept write address when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_awready <= 1'b1;
+ end
+ else
+ begin
+ axi_awready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_awaddr latching
+ // This process is used to latch the address when both
+ // S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awaddr <= 0;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
+ begin
+ // Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end
+ end
+ end
+
+ // Implement axi_wready generation
+ // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_wready <= 1'b0;
+ end
+ else
+ begin
+ if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
+ begin
+ // slave is ready to accept write data when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_wready <= 1'b1;
+ end
+ else
+ begin
+ axi_wready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and write logic generation
+ // The write data is accepted and written to memory mapped registers when
+ // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ // select byte enables of slave registers while writing.
+ // These registers are cleared when reset (active low) is applied.
+ // Slave register write enable is asserted when valid address and data are available
+ // and the slave is ready to accept the write address and write data.
+ assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ slv_reg0 <= 32'b0_1111_11_10_01_00_11_10_01_00;
+ slv_reg1 <= 0;
+ slv_reg2 <= 0;
+ slv_reg3 <= 0;
+ end
+ else begin
+ if (slv_reg_wren)
+ begin
+ case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+ 2'h0:
+ for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+ if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+ // Respective byte enables are asserted as per write strobes
+ // Slave register 0
+ slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+ end
+ 2'h1:
+ for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+ if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+ // Respective byte enables are asserted as per write strobes
+ // Slave register 1
+ slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+ end
+ 2'h2:
+ for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+ if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+ // Respective byte enables are asserted as per write strobes
+ // Slave register 2
+ slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+ end
+ 2'h3:
+ for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
+ if ( S_AXI_WSTRB[byte_index] == 1 ) begin
+ // Respective byte enables are asserted as per write strobes
+ // Slave register 3
+ slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
+ end
+ default : begin
+ slv_reg0 <= slv_reg0;
+ slv_reg1 <= slv_reg1;
+ slv_reg2 <= slv_reg2;
+ slv_reg3 <= slv_reg3;
+ end
+ endcase
+ end
+ end
+ end
+
+ // Implement write response logic generation
+ // The write response and response valid signals are asserted by the slave
+ // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ // This marks the acceptance of address and indicates the status of
+ // write transaction.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_bvalid <= 0;
+ axi_bresp <= 2'b0;
+ end
+ else
+ begin
+ if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+ begin
+ // indicates a valid write response is available
+ axi_bvalid <= 1'b1;
+ axi_bresp <= 2'b0; // 'OKAY' response
+ end // work error responses in future
+ else
+ begin
+ if (S_AXI_BREADY && axi_bvalid)
+ //check if bready is asserted while bvalid is high)
+ //(there is a possibility that bready is always asserted high)
+ begin
+ axi_bvalid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ // Implement axi_arready generation
+ // axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ // S_AXI_ARVALID is asserted. axi_awready is
+ // de-asserted when reset (active low) is asserted.
+ // The read address is also latched when S_AXI_ARVALID is
+ // asserted. axi_araddr is reset to zero on reset assertion.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_arready <= 1'b0;
+ axi_araddr <= 32'b0;
+ end
+ else
+ begin
+ if (~axi_arready && S_AXI_ARVALID)
+ begin
+ // indicates that the slave has acceped the valid read address
+ axi_arready <= 1'b1;
+ // Read address latching
+ axi_araddr <= S_AXI_ARADDR;
+ end
+ else
+ begin
+ axi_arready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_arvalid generation
+ // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ // data are available on the axi_rdata bus at this instance. The
+ // assertion of axi_rvalid marks the validity of read data on the
+ // bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ // is deasserted on reset (active low). axi_rresp and axi_rdata are
+ // cleared to zero on reset (active low).
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rvalid <= 0;
+ axi_rresp <= 0;
+ end
+ else
+ begin
+ if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+ begin
+ // Valid read data is available at the read data bus
+ axi_rvalid <= 1'b1;
+ axi_rresp <= 2'b0; // 'OKAY' response
+ end
+ else if (axi_rvalid && S_AXI_RREADY)
+ begin
+ // Read data is accepted by the master
+ axi_rvalid <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and read logic generation
+ // Slave register read enable is asserted when valid address is available
+ // and the slave is ready to accept the read address.
+ assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+ always @(*)
+ begin
+ // Address decoding for reading registers
+ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+ 2'h0 : reg_data_out <= slv_reg0;
+ 2'h1 : reg_data_out <= slv_reg1;
+ 2'h2 : reg_data_out <= slv_reg2;
+ 2'h3 : reg_data_out <= slv_reg3;
+ default : reg_data_out <= 0;
+ endcase
+ end
+
+ // Output register or memory read data
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rdata <= 0;
+ end
+ else
+ begin
+ // When there is a valid read address (S_AXI_ARVALID) with
+ // acceptance of read address by the slave (axi_arready),
+ // output the read dada
+ if (slv_reg_rden)
+ begin
+ axi_rdata <= reg_data_out; // register read data
+ end
+ end
+ end
+
+ // Add user logic here
+ cross_impl #() cross_inst
+ (
+ .can_rx(can_rx),
+ .can_tx(can_tx),
+ .ifc_rx(ifc_rx),
+ .ifc_tx(ifc_tx),
+ .can_stby(can_stby),
+ .ctrl_word(slv_reg0)
+ );
+ // User logic ends
+
+ endmodule
--- /dev/null
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox]
+ set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH}
+ set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}]
+ set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH}
+ ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_S00_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_S00_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+ # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } {
+ # Procedure called to validate C_S00_AXI_BASEADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+ # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } {
+ # Procedure called to validate C_S00_AXI_HIGHADDR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH}
+}
+
projects / fpga / zynq / canbench-sw.git / commitdiff