]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/blob - system/ip/can_crossbar_1.0/example_designs/debug_hw_design/can_crossbar_v1_0_hw_test.tcl
system: added CAN crossbar IP
[fpga/zynq/canbench-sw.git] / system / ip / can_crossbar_1.0 / example_designs / debug_hw_design / can_crossbar_v1_0_hw_test.tcl
1 # Runtime Tcl commands to interact with - can_crossbar_v1_0
2
3 # Sourcing design address info tcl
4 set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
5 source ${bd_path}/can_crossbar_v1_0_include.tcl
6
7 # jtag axi master interface hardware name, change as per your design.
8 set jtag_axi_master hw_axi_1
9 set ec 0
10
11 # hw test script
12 # Delete all previous axis transactions
13 if { [llength [get_hw_axi_txns -quiet]] } {
14         delete_hw_axi_txn [get_hw_axi_txns -quiet]
15 }
16
17
18 # Test all lite slaves.
19 set wdata_1 abcd1234
20
21 # Test: S00_AXI
22 # Create a write transaction at s00_axi_addr address
23 create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1
24 # Create a read transaction at s00_axi_addr address
25 create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr
26 # Initiate transactions
27 run_hw_axi r_s00_axi_addr
28 run_hw_axi w_s00_axi_addr
29 run_hw_axi r_s00_axi_addr
30 set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]]
31 # Compare read data
32 if { $rdata_tmp == $wdata_1 } {
33         puts "Data comparison test pass for - S00_AXI"
34 } else {
35         puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp"
36         inc ec
37 }
38
39 # Check error flag
40 if { $ec == 0 } {
41          puts "PTGEN_TEST: PASSED!" 
42 } else {
43          puts "PTGEN_TEST: FAILED!" 
44 }
45