]> rtime.felk.cvut.cz Git - fpga/virtex2/uart.git/commit
+ PWM output capability.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Sat, 12 Feb 2011 22:46:34 +0000 (23:46 +0100)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Sun, 13 Feb 2011 12:46:28 +0000 (13:46 +0100)
commite46674ac277a1a88f8e0bcab9d52e683b1603fee
treea9139c0ba93dbb6bb383fd9da66b6c59ef9fee99
parentbecb341a3d46f3a6458ce87a4f531f81e03e84b2
+ PWM output capability.

Added 2 new entities: counter and omsp_pwm.
Instances of these are inserted in the top-level.
counter.vhd [new file with mode: 0644]
omsp_pwm.vhd [new file with mode: 0644]
openMSP430_uart.prj
openMSP430_uart.ucf
openMSP430_uart.vhd