+ PWM output capability.

[fpga/virtex2/uart.git] / openMSP430_uart.ucf

diff --git a/openMSP430_uart.ucf b/openMSP430_uart.ucf
index ae1106c9a3b3d51798f4d66b1da3ab0f55d6275e..a17400a21179e264a83c226fac133f23db334841 100644 (file)
--- a/openMSP430_uart.ucf
+++ b/openMSP430_uart.ucf
@@ -11,6 +11,23 @@ NET "RESET"             LOC = "B6";
 # RS-232 Port                                                                  #
 #==============================================================================#
 
-NET "RXD"               LOC = "A7";     # input to RS232 driver
-NET "TXD"               LOC = "B7";     # output from RS232 driver
+NET "TXD"               LOC = "A7";     # output from the board (from FPGA)
+NET "RXD"               LOC = "B7";     # input to the board (to FPGA)
+
+#==============================================================================#
+# Incremental rotary encoder                                                   #
+#==============================================================================#
+# Connected to the header J4.
+
+NET "ROT_FEED"          LOC = "H2";                 # pin 01
+NET "ROT_A"             LOC = "J2"    | PULLDOWN;   # pin 03
+NET "ROT_B"             LOC = "K2"    | PULLDOWN;   # pin 05
+NET "ROT_PRESS"         LOC = "E4"    | PULLDOWN;   # pin 07
+
+#==============================================================================#
+# PWM output                                                                   #
+#==============================================================================#
+# Connected to the header J7 (LVDS TX STATUS).
+
+NET "PWM"               LOC = "C1";                 # pin 01