+ PWM output capability.

[fpga/virtex2/uart.git] / counter.vhd

diff --git a/counter.vhd b/counter.vhd
new file mode 100644 (file)
index 0000000..cfb698a
--- /dev/null
+++ b/counter.vhd
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+--------------------------------------------------------------------------------
+-- General counter which count width and maximum value can be set by generic
+-- attributes.
+--------------------------------------------------------------------------------
+
+entity counter is
+  generic (
+    WIDTH : integer := 16;
+    MAX   : integer := 2**16 - 1);
+  port (
+    clk   : in  std_logic;
+    reset : in  std_ulogic;
+    count : out std_logic_vector (WIDTH-1 downto 0));
+end counter;
+
+--------------------------------------------------------------------------------
+
+architecture behavioral of counter is
+
+  signal cnt : std_logic_vector (WIDTH-1 downto 0);
+
+--------------------------------------------------------------------------------
+
+begin
+
+  count <= cnt;
+  
+  
+  process (clk, reset) is
+  begin
+    if reset = '1' then
+      cnt <= (others => '0');
+
+    elsif clk'event and clk = '1' then
+      if cnt = CONV_STD_LOGIC_VECTOR(MAX, WIDTH) then
+        cnt <= (others => '0');
+      else
+        cnt <= cnt + 1;
+      end if;
+    end if;
+  end process;
+
+end behavioral;
+