New HW UART submodule added.

[fpga/virtex2/uart.git] / openMSP430_uart.prj

diff --git a/openMSP430_uart.prj b/openMSP430_uart.prj
index d17fdd7bf7289e464a038b1a65ae7b7c1676b440..d13221438e43b8b77f580a52ec0fddc9bac23d4d 100644 (file)
--- a/openMSP430_uart.prj
+++ b/openMSP430_uart.prj
@@ -19,6 +19,10 @@ verilog work openMSP430_defines.v
 verilog work openmsp430/periph/omsp_gpio.v
 verilog work openmsp430/periph/omsp_timerA.v
 
+vhdl work omsp_quadcount.vhd
+vhdl work quadcount/dff.vhdl
+vhdl work quadcount/qcounter.vhdl
+
 vhdl work coregen/ram_8x512.vhd
 vhdl work coregen/rom_8x2k.vhd