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New HW UART submodule added.
[fpga/virtex2/uart.git] / uart
diff --git a/uart b/uart
new file mode 160000 (submodule)
index 0000000..81d3090
--- /dev/null
+++ b/uart
@@ -0,0 +1 @@
+Subproject commit 81d30909cb24a0f382a045c90f11444dd35cc1cf
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board