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Copied all needed files.
[fpga/virtex2/uart.git] / coregen / ram_8x512_flist.txt
1 # Output products list for <ram_8x512>
2 ram_8x512.vho
3 ram_8x512.asy
4 ram_8x512.sym
5 ram_8x512_xmdf.tcl
6 ram_8x512_flist.txt
7 ram_8x512.vhd
8 ram_8x512.ngc
9 ram_8x512.xco
MSP430 simple UART echo - test top level design for Virtex 2 V2MB1000 board