2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_ARITH.ALL;
4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 entity omsp_quadcount is
9 per_addr : in std_logic_vector (7 downto 0);
10 per_din : in std_logic_vector (15 downto 0); -- unused
11 per_en : in std_logic;
12 per_wen : in std_logic_vector (1 downto 0); -- unused
13 puc : in std_logic; -- unused
14 per_irq_acc : in std_logic; -- unused
15 per_irq : out std_logic;
16 per_dout : out std_logic_vector (15 downto 0);
18 qcount : in std_logic_vector (31 downto 0)
22 --------------------------------------------------------------------------------
24 architecture behavioral of omsp_quadcount is
26 -- When reading whole 32-bit qcount input, first QCNTL has to be loaded, because
27 -- this event causes QCNTH to latch appropriate value of qcount. This procedure
28 -- ensures that correct value is readed.
29 constant QCNTL : std_logic_vector (15 downto 0) := X"0150"; -- qcount lower word logic address
30 constant QCNTH : std_logic_vector (15 downto 0) := X"0152"; -- qcount higher word logic address
32 signal qcntl_sel : boolean;
33 signal qcnth_sel : boolean;
35 signal qcnth_latch : std_logic_vector (15 downto 0) := (others => '0');
37 signal qcount_prev : std_logic_vector (31 downto 0) := (others => '0');
39 --------------------------------------------------------------------------------
43 qcntl_sel <= (per_addr = QCNTL(8 downto 1)) and (per_en = '1');
44 qcnth_sel <= (per_addr = QCNTH(8 downto 1)) and (per_en = '1');
46 per_dout <= qcount (15 downto 0) when qcntl_sel else
47 qcnth_latch when qcnth_sel else
53 if (rising_edge(mclk) and qcntl_sel) then
54 qcnth_latch <= qcount (31 downto 16);
58 -- Generation of IRQ signal. (changes in lower 2 bits are suppresed)
61 if (rising_edge(mclk)) then
62 qcount_prev <= qcount;
66 elsif (qcount_prev (31 downto 2) /= qcount (31 downto 2)) then