1 --------------------------------------------------------------------------------
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26 -- (c) Copyright 1995-2007 Xilinx, Inc. --
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28 --------------------------------------------------------------------------------
29 -- You must compile the wrapper file rom_8x2k.vhd when simulating
30 -- the core, rom_8x2k. When compiling the wrapper file, be sure to
31 -- reference the XilinxCoreLib VHDL simulation library. For detailed
32 -- instructions, please refer to the "CORE Generator Help".
34 -- The synthesis directives "translate_off/translate_on" specified
35 -- below are supported by Xilinx, Mentor Graphics and Synplicity
36 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
39 USE ieee.std_logic_1164.ALL;
40 -- synthesis translate_off
41 Library XilinxCoreLib;
42 -- synthesis translate_on
45 addr: IN std_logic_VECTOR(10 downto 0);
47 din: IN std_logic_VECTOR(7 downto 0);
48 dout: OUT std_logic_VECTOR(7 downto 0);
53 ARCHITECTURE rom_8x2k_a OF rom_8x2k IS
54 -- synthesis translate_off
55 component wrapped_rom_8x2k
57 addr: IN std_logic_VECTOR(10 downto 0);
59 din: IN std_logic_VECTOR(7 downto 0);
60 dout: OUT std_logic_VECTOR(7 downto 0);
65 -- Configuration specification
66 for all : wrapped_rom_8x2k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
71 c_yclk_is_rising => 1,
72 c_ysinit_is_high => 1,
74 c_yprimitive_type => "16kx1",
75 c_ytop_addr => "1024",
76 c_yhierarchy => "hierarchy1",
77 c_has_limit_data_pitch => 0,
81 c_yuse_single_primitive => 0,
87 c_ybottom_addr => "0",
91 c_has_default_data => 1,
92 c_limit_data_pitch => 18,
94 c_yydisable_warnings => 1,
95 c_mem_init_file => "mif_file_16_1",
96 c_default_data => "0",
99 -- synthesis translate_on
101 -- synthesis translate_off
102 U0 : wrapped_rom_8x2k
110 -- synthesis translate_on