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Reset changed to use Global Set Reset network.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:40:56 +0000 (23:40 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:40:56 +0000 (23:40 +0200)
Resets are coming only from outside of FPGA and are realized
by STARTUP_VIRTEX2 component. No other reset network is present
so the design is smaller (-86 LUT4, approx 3%). But hardware cannot
be reset form softcore MCU.


No differences found
MSP430 BLDC control HW and PXMC SW - top level design for Virtex 2 V2MB1000 board