]> rtime.felk.cvut.cz Git - fpga/virtex2/msp_motion.git/commitdiff
Reset changed to use Global Set Reset network.
authorVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:40:56 +0000 (23:40 +0200)
committerVladimir Burian <buriavl2@fel.cvut.cz>
Wed, 18 May 2011 21:40:56 +0000 (23:40 +0200)
Resets are coming only from outside of FPGA and are realized
by STARTUP_VIRTEX2 component. No other reset network is present
so the design is smaller (-86 LUT4, approx 3%). But hardware cannot
be reset form softcore MCU.

msp_motion.vhd

index 2d2f3f496a1ca2ff11644cb8252c38bb6d49a748..2e949871860b00ac85c56a9af05dc877d2527506 100644 (file)
@@ -41,6 +41,8 @@ end msp_motion;
 
 architecture rtl of msp_motion is
 
+  signal reset_p : std_logic;
+
   ------------------------------------------------------------------------------
   -- OpenMSP430 softcore MCU module
   ------------------------------------------------------------------------------
@@ -142,7 +144,7 @@ begin
     port map (
       dco_clk                  => CLK_24MHz,
       lfxt_clk                 => '0',
-      reset_n                  => RESET,
+      reset_n                  => '1',
       rxd                      => RXD,
       txd                      => TXD,
       per_addr                 => per_addr,
@@ -156,13 +158,24 @@ begin
       aclk_en                  => open,
       smclk_en                 => open,
       mclk                     => mclk,
-      puc                      => puc,
+      puc                      => open,
       dmem_addr                => dmem_addr,
       dmem_ce                  => dmem_ce,
       dmem_we                  => dmem_we,
       dmem_din                 => dmem_din,
       dmem_dout                => dmem_dout);
 
+  puc     <= '0';
+  reset_p <= not RESET;
+
+  STARTUP_VIRTEX2_inst : STARTUP_VIRTEX2
+    port map (
+      CLK => open,
+      -- Clock input for start-up sequence
+      GSR => reset_p, -- Global Set/Reset input (GSR cannot be used for the port name)
+      GTS => open); -- Global 3-state input (GTS cannot be used for the port name)
+
+
   -- External data bus address decoder and data multiplexer.
   ------------------------------------------------------------------------------
   -- When connection more memories, be aware that 'dmem_dout' can vary only when