From a168a3efb68bc9daad5515401a94450b08689053 Mon Sep 17 00:00:00 2001 From: Vladimir Burian Date: Fri, 4 Feb 2011 11:27:30 +0100 Subject: [PATCH] RX modul synchronization changed to falling edges. --- rx.vhd | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/rx.vhd b/rx.vhd index 5a7bde6..11dc9d9 100644 --- a/rx.vhd +++ b/rx.vhd @@ -12,13 +12,14 @@ use ieee.std_logic_unsigned.all; -- -- Receiving is done by the following procedure: -- - wait until 'ready' = 1 --- - set 'en' and raise 'clk' positive edge (1st bit is sampled) +-- - set 'en' and make 'clk' falling edge (1st bit is sampled) -- - 'ready' goes to 0 -- - continue generating clock signal until 'ready' = 1 again -- - frame is received -- -- All operations, 'rx' sampling, etc. (except for reset) are synchronous to --- 'clk' rising egdes. +-- 'clk' !!! FALLING !!! egdes. The reason is that sampling should occurs in the +-- middle of period where usally clock signal is falling. -- -- Invalid start bit is signalized at the begining of the frame, so the -- receiving can be immediately stopped by receiver reset. @@ -58,7 +59,7 @@ begin bad_stop_bit <= '0'; bad_start_bit <= '0'; - elsif clk'event and clk = '1' then + elsif clk'event and clk = '0' then -- Start receiving a new frame if rx_ready = '1' and en = '1' then rx_shift_reg <= rx & rx_shift_reg (9 downto 1); -- 2.39.2