X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/uart.git/blobdiff_plain/81d30909cb24a0f382a045c90f11444dd35cc1cf..6ce709d167d1e0f4b0ab62ad931b737ea781136a:/rx_control.vhd

diff --git a/rx_control.vhd b/rx_control.vhd
index ad10c6d..80904fa 100644
--- a/rx_control.vhd
+++ b/rx_control.vhd
@@ -11,10 +11,10 @@ entity rx_control is
     bad_start_bit : in  std_logic;
     bad_stop_bit  : in  std_logic;
     rx_ready      : in  std_logic;
-    rx_reset      : out std_logic;
-    rx_en         : out std_logic;
-    fifo_we       : out std_logic;
-    clk_en        : out std_logic);
+    rx_reset      : out std_logic := '0';
+    rx_en         : out std_logic := '0';
+    fifo_we       : out std_logic := '0';
+    clk_en        : out std_logic := '0');
 end entity rx_control;
 
 --------------------------------------------------------------------------------
@@ -23,7 +23,7 @@ architecture behavioral of rx_control is
 
   type state_t is (resetting, waiting, next_frame, receiving);
 
-  signal state : state_t;
+  signal state : state_t := waiting;
 
 --------------------------------------------------------------------------------