2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
10 tx_ready : in std_logic;
11 fifo_empty : in std_logic;
12 tx_we : out std_logic;
13 fifo_pop : out std_logic
17 --------------------------------------------------------------------------------
19 architecture behavioral of tx_control is
21 type state_t is (waiting, next_frame, transmitting);
23 signal state : state_t;
25 --------------------------------------------------------------------------------
34 elsif (rising_edge(clk)) then
37 if (fifo_empty = '0') then
42 if (tx_ready = '0') then
43 state <= transmitting;
47 if (tx_ready = '1') then
48 if (fifo_empty = '0') then
59 process (state, tx_ready)
68 if (tx_ready = '0') then
80 --------------------------------------------------------------------------------