2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
8 output_fifo_width : integer := 2
12 per_addr : in std_logic_vector (7 downto 0);
13 per_din : in std_logic_vector (15 downto 0); -- unused
14 per_en : in std_logic;
15 per_wen : in std_logic_vector (1 downto 0); -- unused
16 puc : in std_logic; -- unused
17 --per_irq_acc : in std_logic; -- unused
18 --per_irq : out std_logic;
19 per_dout : out std_logic_vector (15 downto 0);
30 -- - TX buffer full .1b
31 -- - TX buffer empty .1b
32 -- - TX buffer empty IE 1.b
35 -- - RX buffer empty .1b
36 -- - RX buffer half full .1b
37 -- - RX buffer full .1b
38 -- - RX buffer half full IE .1b
39 -- - RX buffer full IE .1b
40 -- - RX framing error .1b
41 -- - RX buffer overflow .1b
43 --------------------------------------------------------------------------------
45 architecture dataflow of uart is
47 component tx_control is
51 tx_ready : in std_logic;
52 fifo_empty : in std_logic;
53 tx_we : out std_logic;
54 fifo_pop : out std_logic
58 component transmitter is
62 data : in std_logic_vector (7 downto 0);
64 ready : out std_logic;
78 clear_ow : in std_logic;
79 d_in : in std_logic_vector (7 downto 0);
80 d_out : out std_logic_vector (7 downto 0);
82 hfull : out std_logic;
83 empty : out std_logic;
84 overflow : out std_logic
92 scale : in std_logic_vector (15 downto 0);
93 clk_baud : out std_logic
97 --------------------------------------------------------------------------------
99 type boolean_vector is array (natural range <>) of boolean;
101 --------------------------------------------------------------------------------
103 constant base_addr : integer := 16#0100#;
105 constant UBAUD : integer := base_addr + 00;
106 constant UTX : integer := base_addr + 02;
108 signal reg_we : std_logic_vector (511 downto 0);
109 signal reg_re : boolean_vector (511 downto 0);
111 signal tx_clk : std_logic;
112 signal tx_data : std_logic_vector (7 downto 0);
113 signal tx_we : std_logic;
114 signal tx_ready : std_logic;
116 signal tx_fifo_empty : std_logic;
117 signal tx_fifo_re : std_logic;
118 signal tx_fifo_we : std_logic;
120 --------------------------------------------------------------------------------
124 process (per_addr, per_wen, per_en)
126 for i in reg_re'range loop
130 if (per_en = '1' and per_addr = i/2) then
133 if (per_wen (i mod 2) = '1') then
141 tx_control_0 : tx_control port map (
144 tx_ready => tx_ready,
145 fifo_empty => tx_fifo_empty,
147 fifo_pop => tx_fifo_re
150 transmitter_0 : transmitter port map (
159 tx_fifo : fifo port map (
165 d_in => per_din (7 downto 0),
169 empty => tx_fifo_empty,
173 baud_gen_0 : baud_gen port map (
176 scale => "0000000000000000",
181 --------------------------------------------------------------------------------
183 tx_fifo_we <= reg_we (UTX);