default_CONFIG += CONFIG_APP_RPI_PMSM_T1_WITH_ULAN=x
default_CONFIG += CONFIG_APP_RPI_PMSM_T1_WITH_SUITK=x
default_CONFIG += CONFIG_APP_RPI_PMSM_T1_WITH_SIM_POSIX=x
+default_CONFIG += CONFIG_APP_RPI_PMSM_T1_WITH_ZYNQ_DRV=x
+default_CONFIG += CONFIG_APP_RPI_PMSM_T1_SETUP_CLKOUT=y
default_CONFIG += CONFIG_OC_CMDPROC=x CONFIG_PXMC=x CONFIG_PXMC_COORDMV=x
ifeq ($(CONFIG_APP_RPI_PMSM_T1),y)
rpi_pmsm_t1_SOURCES += appl_utils.c
+ifneq ($(CONFIG_APP_RPI_PMSM_T1_WITH_ZYNQ_DRV),y)
rpi_pmsm_t1_SOURCES += rpi_gpio.c
rpi_pmsm_t1_SOURCES += rpi_gpclk.c
rpi_pmsm_t1_SOURCES += rpi_spi.c
+else
+rpi_pmsm_t1_SOURCES += zynq_3pmdrv1_mc.c
+endif
ifeq ($(CONFIG_OC_CMDPROC),y)
rpi_pmsm_t1_SOURCES += appl_cmdproc.c
#include "appl_config.h"
+#ifdef CONFIG_APP_ROCON_WITH_SUITK
+#define APPL_WITH_SUITK
+#endif /*CONFIG_APP_ROCON_WITH_SUITK*/
+
+#ifdef CONFIG_APP_RPI_PMSM_T1_WITH_ZYNQ_DRV
+#define APPL_WITH_ZYNQ_DRV
+#endif /*CONFIG_APP_RPI_PMSM_T1_WITH_ZYNQ_DRV*/
+
+#ifdef CONFIG_APP_RPI_PMSM_T1_SETUP_CLKOUT
+#define APPL_RPI_PMSM_SETUP_CLKOUT
+#endif /*CONFIG_APP_RPI_PMSM_T1_SETUP_CLKOUT*/
+
#include <stdint.h>
/*
#include "appl_defs.h"
#include "appl_utils.h"
+
+#ifdef APPL_WITH_ZYNQ_DRV
+#include "zynq_3pmdrv1_mc.h"
+#else
#include "rpi_gpio.h"
#include "rpi_gpclk.h"
+#endif
void appl_stop(void)
{
fprintf(stderr, "Application abnormal termination\n");
sleep(1);
/* stop clock pin driving FPGA to ensure failase state */
+ #ifndef APPL_WITH_ZYNQ_DRV
rpi_gpio_direction_output(4, 0);
+ #endif
}
/***********************************/
{
appl_setup_environment(argv[0]);
+#ifdef APPL_RPI_PMSM_SETUP_CLKOUT
+
/* initialize 50 Mhz clock output on gpio 4 */
if (rpi_peripheral_registers_map() < 0) {
fprintf(stderr, "%s: rpi_peripheral_registers_map failed\n", argv[0]);
return -1;
}
+#endif /* APPL_RPI_PMSM_SETUP_CLKOUT */
+
pxmc_initialize();
do {
#include "appl_pxmc.h"
#include "appl_utils.h"
+#ifdef APPL_WITH_ZYNQ_DRV
+#include "zynq_3pmdrv1_mc.h"
+typedef z3pmdrv1_state_t spimc_state_t;
+#define SPIMC_PWM_ENABLE Z3PMDRV1_PWM_ENABLE
+#define SPIMC_PWM_SHUTDOWN Z3PMDRV1_PWM_SHUTDOWN
+#define SPIMC_CHAN_COUNT Z3PMDRV1_CHAN_COUNT
+#define spimc_transfer z3pmdrv1_transfer
+#define spimc_init z3pmdrv1_init
+#else
#include "pxmc_spimc.h"
+#endif
pthread_t pxmc_base_thread_id;
return 0;
}
+
spimc_state_t spimc_state0 = {
- .spi_dev = "/dev/spidev0.1",
+ #ifndef APPL_WITH_ZYNQ_DRV
+ //.spi_dev = "/dev/spidev0.1",
+ .spi_dev = "/dev/spidev1.0",
+ #endif /*APPL_WITH_ZYNQ_DRV*/
};
pxmc_spimc_state_t mcs0 =
#include <pxmc.h>
struct spimc_state_t;
+struct z3pmdrv1_state_t;
typedef struct pxmc_spimc_state_t {
pxmc_state_t base;
+ #ifdef APPL_WITH_ZYNQ_DRV
+ struct z3pmdrv1_state_t *spimc_state;
+ #else
struct spimc_state_t *spimc_state;
+ #endif
uint32_t steps_pos_prev;
uint32_t cur_d_cum_prev;
uint32_t cur_q_cum_prev;
#include "appl_defs.h"
#include "appl_pxmc.h"
+
+#ifdef APPL_WITH_ZYNQ_DRV
+#include "zynq_3pmdrv1_mc.h"
+typedef z3pmdrv1_state_t spimc_state_t;
+#define SPIMC_PWM_ENABLE Z3PMDRV1_PWM_ENABLE
+#define SPIMC_PWM_SHUTDOWN Z3PMDRV1_PWM_SHUTDOWN
+#define SPIMC_CHAN_COUNT Z3PMDRV1_CHAN_COUNT
+#else
#include "pxmc_spimc.h"
+#endif
#define SPIMC_LOG_CURRENT_SIZE 1024*1024
pxmc_dbgset(mcs, NULL, 0);
spimc_currentcal_setup(spimc, cucalst, skip_accum,
pwm1, pwm1_en, pwm2, pwm2_en, pwm3, pwm3_en);
+
+ printf("cycle %d\n",cycle);
+ char buff[10];
+ fgets(buff, 9, stdin);
+
pxmc_dbgset(mcs, spimc_currentcal_accum, 1);
sem_wait(&spimc_currentcal_sem);