]> rtime.felk.cvut.cz Git - fpga/lx-cpu1/tumbl.git/commit
Add halt and wire out bad op signal
authorMartin Meloun <meloumar@cmp.felk.cvut.cz>
Fri, 6 Sep 2013 10:06:23 +0000 (12:06 +0200)
committerMartin Meloun <meloumar@cmp.felk.cvut.cz>
Fri, 6 Sep 2013 10:06:23 +0000 (12:06 +0200)
commitb7529be7741c46ef603ef0e487642a065f3a998a
tree20593f048cd17dbfd05f5a9f908dfb23907fa4a0
parent342b65f43eca19d8169829aa8d342d1424c6d323
Add halt and wire out bad op signal

Signed-off-by: Martin Meloun <meloumar@cmp.felk.cvut.cz>
hw/core_ctrl.vhd
hw/decode.vhd
hw/fetch.vhd
hw/mbl_Pkg.vhd