Add halt and wire out bad op signal

[fpga/lx-cpu1/tumbl.git] / hw / decode.vhd

diff --git a/hw/decode.vhd b/hw/decode.vhd
index bee212b1bbfda85415f911e6082254aaeb48ae88..b9004590f89084af80734b7209943f2529ad7b5e 100644 (file)
--- a/hw/decode.vhd
+++ b/hw/decode.vhd
@@ -36,7 +36,9 @@ ENTITY decode IS
         ID2EX_o     : OUT ID2EX_Type;
         --
         INT_CTRL_i  :  IN INT_CTRL_Type;
-        ID2CTRL_o   : OUT ID2CTRL_Type
+        ID2CTRL_o   : OUT ID2CTRL_Type;
+                               --
+                               noLiteOpc_s : OUT STD_LOGIC
         );
 END ENTITY decode;
 
@@ -45,8 +47,6 @@ END ENTITY decode;
 ARCHITECTURE rtl OF decode IS
 --------------------------------------------------------------------------------
 
-    SIGNAL noLiteOpc_s : STD_LOGIC;
-
 BEGIN
 
 p_decode: