Add halt and wire out bad op signal

[fpga/lx-cpu1/tumbl.git] / hw / fetch.vhd

diff --git a/hw/fetch.vhd b/hw/fetch.vhd
index 08722934c688f9f637928938a15b60ed57afba0d..359f8164527db6d4ce162f160793150da7e95ee3 100644 (file)
--- a/hw/fetch.vhd
+++ b/hw/fetch.vhd
@@ -40,10 +40,9 @@ p_fetch:
     PROCESS ( prog_cntr_i, inc_pc_i, EX2IF_i )
         VARIABLE next_pc_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
         VARIABLE incVal_v  : STD_LOGIC_VECTOR (31 DOWNTO 0);
-        VARIABLE dummy_v   : STD_LOGIC;
     BEGIN
         incVal_v := X"0000000" & '0' & inc_pc_i & "00";
-        ep_add32 ( prog_cntr_i, incVal_v, '0', next_pc_v, dummy_v);
+        ep_add32nc ( prog_cntr_i, incVal_v, '0', next_pc_v );
         IF (EX2IF_i.take_branch = '0') THEN
             IF2ID_o.program_counter <= next_pc_v;
         ELSE