use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
-use work.mbl_pkg.all;
use work.lx_rocon_pkg.all;
-- IRC bus interconnect
reset_i : in std_logic;
-- Data bus
address_i : in std_logic_vector(4 downto 0);
- next_ce_i : in std_logic;
+ ce_i : in std_logic;
data_i : in std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
--
architecture Behavioral of bus_irc is
- signal irc_o_s : IRC_OUTPUT_Array_Type(7 downto 0);
- signal reset_index_event_s : std_logic_vector(7 downto 0);
- signal reset_index_event2_s : std_logic_vector(7 downto 0);
- signal reset_ab_error_s : std_logic_vector(7 downto 0);
+ constant num_irc_c : positive := 8;
+
+ signal irc_o_s : IRC_OUTPUT_Array_Type(num_irc_c-1 downto 0);
+ signal irc_count_s : IRC_COUNT_OUTPUT_Array_Type((num_irc_c-1) downto 0);
+
+ signal reset_index_event_s : std_logic_vector(num_irc_c-1 downto 0);
+ signal reset_index_event2_s : std_logic_vector(num_irc_c-1 downto 0);
+ signal reset_ab_error_s : std_logic_vector(num_irc_c-1 downto 0);
signal state_o_s : std_logic_vector(3 downto 0);
signal state_o_r : std_logic_vector(3 downto 0);
--
signal reset_reg_wr_s : std_logic;
--
signal reset_s : std_logic;
- signal ce_s : std_logic;
+ signal ce_r : std_logic;
begin
-irc0 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(0),
- reset_index_event_i => reset_index_event_s(0),
- reset_index_event2_i => reset_index_event2_s(0),
- reset_ab_error_i => reset_ab_error_s(0),
- irc_o => irc_o_s(0)
- );
-
-irc1 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(1),
- reset_index_event_i => reset_index_event_s(1),
- reset_index_event2_i => reset_index_event2_s(1),
- reset_ab_error_i => reset_ab_error_s(1),
- irc_o => irc_o_s(1)
- );
-
-irc2 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(2),
- reset_index_event_i => reset_index_event_s(2),
- reset_index_event2_i => reset_index_event2_s(2),
- reset_ab_error_i => reset_ab_error_s(2),
- irc_o => irc_o_s(2)
- );
-
-irc3 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(3),
- reset_index_event_i => reset_index_event_s(3),
- reset_index_event2_i => reset_index_event2_s(3),
- reset_ab_error_i => reset_ab_error_s(3),
- irc_o => irc_o_s(3)
- );
-
-irc4 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(4),
- reset_index_event_i => reset_index_event_s(4),
- reset_index_event2_i => reset_index_event2_s(4),
- reset_ab_error_i => reset_ab_error_s(4),
- irc_o => irc_o_s(4)
- );
-
-irc5 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(5),
- reset_index_event_i => reset_index_event_s(5),
- reset_index_event2_i => reset_index_event2_s(5),
- reset_ab_error_i => reset_ab_error_s(5),
- irc_o => irc_o_s(5)
- );
-
-irc6 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(6),
- reset_index_event_i => reset_index_event_s(6),
- reset_index_event2_i => reset_index_event2_s(6),
- reset_ab_error_i => reset_ab_error_s(6),
- irc_o => irc_o_s(6)
- );
-
-irc7 : irc_reader
- port map
- (
- clk_i => clk_i,
- reset_i => reset_s,
- irc_i => irc_i(7),
- reset_index_event_i => reset_index_event_s(7),
- reset_index_event2_i => reset_index_event2_s(7),
- reset_ab_error_i => reset_ab_error_s(7),
- irc_o => irc_o_s(7)
- );
+irc_generate: for i in 0 to num_irc_c-1 generate
+ irc : irc_reader
+ port map
+ (
+ clk_i => clk_i,
+ reset_i => reset_s,
+ irc_i => irc_i(i),
+ reset_index_event_i => reset_index_event_s(i),
+ reset_index_event2_i => reset_index_event2_s(i),
+ reset_ab_error_i => reset_ab_error_s(i),
+ irc_o => irc_o_s(i)
+ );
+
+ irc_count_s(i) <= irc_o_s(i).count;
+ end generate;
irc_proc : irc_proc_main
generic map
(
- num_irc_g => 8
+ num_irc_g => num_irc_c
)
port map
(
clk_i => clk_i,
reset_i => reset_s,
-- IRC
- irc_i(0) => irc_o_s(0).count,
- irc_i(1) => irc_o_s(1).count,
- irc_i(2) => irc_o_s(2).count,
- irc_i(3) => irc_o_s(3).count,
- irc_i(4) => irc_o_s(4).count,
- irc_i(5) => irc_o_s(5).count,
- irc_i(6) => irc_o_s(6).count,
- irc_i(7) => irc_o_s(7).count,
+ irc_i => irc_count_s,
irc_index_reset_o => reset_index_event_s,
-- BRAM
mem_clk_i => clk_i,
reset_s <= reset_reg_r or reset_i;
wire_in:
- process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
+ process(ce_i, ce_r, reset_reg_r, bls_i, address_i, irc_data_s, data_i, irc_o_s)
begin
-- init values
reset_reg_wr_s <= '0';
-- Incoming bus request
- if next_ce_i = '1' then
+ if ce_i = '1' then
-- Mapping:
-- 0 & axis & irc / index - (all read from bram) (R/W)
-- 1 & axis & 0 - status register (R/W)
irc_bls_s <= bls_i;
irc_out_s <= '1';
- -- Maybe these would be better to latch in next_ce_i cycle,
+ -- Maybe these would be better to latch in ce_i cycle,
-- and then just pass them
elsif address_i(0) = '0' then
end process;
wire_out:
- process(ce_s, irc_data_s, irc_out_r, state_o_r)
+ process(ce_r, irc_data_s, irc_out_r, state_o_r)
begin
data_o <= (others => '0');
- if ce_s = '1' then
+ if ce_r = '1' then
if irc_out_r = '1' then
data_o <= irc_data_s;
process
begin
wait until clk_i'event and clk_i= '1';
- ce_s <= next_ce_i;
+ ce_r <= ce_i;
irc_out_r <= irc_out_s;
state_o_r <= state_o_s;
projects / fpga / lx-cpu1 / lx-rocon.git / blobdiff