4 * Program to test DTC unit using the dtcvec library.
5 * Copy from src to dest on the interrupt of TPU_TGR3A.
7 * Tested board: Mirosot with Hitachi processor H8S/2638
9 * Copyright: (c) 2007 CTU Dragons
10 * CTU FEE - Department of Control Engineering
11 * Contacts: Tran Duy Khanh <trandk1@fel.cvut.cz>
12 * License: GNU GPL v.2
15 /* procesor H8S/2638 ver 1.1 */
18 #include <system_def.h>
20 #include <periph/sci_rs232.h>
26 static __u16 dest = 0;
28 /* register information vector */
34 /* Manipulation with diagnostic leds */
35 void deb_led_out(char val)
37 if (val&1) DEB_LED_ON(0); else DEB_LED_OFF(0);
38 if (val&2) DEB_LED_ON(1); else DEB_LED_OFF(1);
39 if (val&4) DEB_LED_ON(2); else DEB_LED_OFF(2);
40 if (val&8) DEB_LED_ON(3); else DEB_LED_OFF(3);
43 /* Unhandled (catch-all) exception */
44 void unhandled_exception(void) __attribute__ ((interrupt_handler));
45 void unhandled_exception(void)
51 * init - shadow registers, outputs..
53 * Initializes P1 and P3 shadow registers, sets PJ.1, PJ.2, PJ.3 LED as
54 * outputs, initialises interrupt vector.
58 /* sets shadow registers */
62 /* sets PJ.1, PJ.2, PJ.3 LED output */
63 *DIO_PJDDR &= ~(PJDDR_PJ1DDRm | PJDDR_PJ2DDRm |PJDDR_PJ3DDRm);
64 SHADOW_REG_SET(DIO_PJDDR,0xee);
67 SHADOW_REG_SET(DIO_P3DDR,0x85);
69 /* initialises interrupt vector */
70 excptvec_initfill(unhandled_exception, 0);
72 /* shows something on debug leds */
77 /* TPU Initialization */
80 *SYS_MSTPCRA &= ~MSTPCRA_TPUm; // power TPU unit
81 *TPU_TSTR &= ~TSTR_CST3m; /*counter n is stoped*/
83 /*CNTN cleared by by TGRA, rising edge; source TGRA compare match/input
84 * capture, prescaler 1024 */
85 *TPU_TCR3 = (TPCR_TPSC_3F4096 | TPCR_CKEG_FAL | TPCR_CCLR_TGRA);
86 /*TGRA is input capture registr at rising edge*/
87 *TPU_TIOR3H |= TIOR3H_IOA3m;
88 /*MDn = 0x000 normal operation */
89 *TPU_TMDR3 = TPMDR_MD_NORMAL;
90 /*TimerStatusRegistr - clear interrupt source */
91 *TPU_TSR3 &= ~TSR3_TGFAm;
92 /*TimerInterruptEnableReg - enable IRQ generation from TGRA and TGRB*/
93 *TPU_TIER3 |= TIER3_TGIEAm;
95 *TPU_TSTR |= TSTR_CST3m;
99 * Initialization of the DTC transfers
103 struct dtcvec_reginfo reginfo;
105 /* allocate memory for register information. The length of each block
107 rivect = (__u32*)dtcvec_alloc(1);
109 /* stop DTC module */
110 *SYS_MSTPCRA |= MSTPCRA_MSTPA6m;
112 /* setup transfer`s register information */
113 reginfo.mra = (MRA_SM_FIXED|MRA_DM_FIXED|MRA_MD_NORMAL|MRA_SZ_WORD);
115 reginfo.sar = (__u32)&src;
116 reginfo.dar = (__u32)&dest;
117 reginfo.cra = 0xffff;
118 reginfo.crb = 0x0000;
119 /* align bytes in the memory */
120 dtcvec_fillreg(rivect, ®info);
121 /* assign DTC vector address */
122 dtcvec_set(DTCVEC_TGI3A, rivect);
124 /* DTC activation for TGI3A */
125 *DTC_DTCERC |= DTCERC_DTCEC5m;
126 /* unblock DTC module */
127 *SYS_MSTPCRA &= ~MSTPCRA_MSTPA6m;
132 /* enable interrupts and serial debug channel */
133 FlWait(3000000);//waiting for serial terminal run
136 sci_rs232_setmode(19200, 0, 0, sci_rs232_chan_default);
140 /* TPU initialization */
142 /* DTC initialization */
148 printf("src = %d; dest = %d\n", src, dest);