#define Dem_ReportErrorStatus(...)\r
#endif\r
\r
-static sint8 IfRegId = 0;\r
+//static sint8 IfRegId = 0;\r
\r
/* Macro for waiting until busy flag is 0 */\r
#define DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId) \\r
static CanIf_ControllerModeType ControllerMode[CAN_ARC_CTRL_CONFIG_CNT];\r
\r
/* Used to switch between IF1 and IF2 of DCAN */\r
+static uint8 IfRegId = 0;\r
+\r
\r
/* Used to order Data Bytes according to hardware registers in DCAN */\r
static const uint8 ElementIndex[] = {3, 2, 1, 0, 7, 6, 5, 4};\r
CanRegs[Controller]->CTL = 0x02001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
#else\r
CanRegs[Controller]->CTL = 0x00001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
+\r
+ /* Parity Off */\r
+ CanRegs[Controller]->CTL = 0x00020043 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8);\r
#endif \r
/* LEC 7, TxOk, RxOk, PER */\r
CanRegs[Controller]->SR = 0x0000011F;\r
+ //CanRegs[Controller]->SR = 0x0000031F; // according to HalCoGen\r
\r
/* Test Mode only for Development time: Silent Loopback */\r
if (CanControllerConfigData[Controller].Can_Arc_Loopback) {\r
*(ControllerConfig[Controller].CancelPtr + MsgNr) = 0;\r
*(ControllerConfig[Controller].TxPtr + MsgNr) = 0;\r
\r
+ CanRegs[Controller]->ABOT = 0; // added manually according to HalCoGen, maybe delete???\r
+\r
DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
\r
// Initialize all message objects for this controller to invalid state.\r
CanRegs[Controller]->IFx[IfRegId].ARB = 0x00000000;\r
/* Start writing Arbitration Bits */\r
CanRegs[Controller]->IFx[IfRegId].COM = 0x00A80000 | (MsgNr + 1);\r
+ // CanRegs[Controller]->IFx[IfRegId].COM = 0x00F80000 | (MsgNr + 1); maybe right, later it's used again??\r
\r
/* Use IFx[0] and IFx[1] alternating */\r
IfRegId ^= 1;\r
| (CanControllerConfigData[Controller].CanTxProcessing << 1) // Tx confirmation interrupt enabled\r
| (Eob & ~(hoh->CanObjectType >> 22)); // Eob, only for Rx.\r
\r
+ //CanRegs[Controller]->IFx[IfRegId].MC = 0x00001008;\r
+\r
//CanRegs[Controller]->IFx[IfRegId].MC = 0x00001008 | CanControllerConfigData[Controller].CanRxProcessing | (CanControllerConfigData[Controller].CanTxProcessing) | Eob & ~(hoh->CanObjectType >> 17);\r
\r
if(hoh->CanIdType == CAN_ID_TYPE_STANDARD) /* Standard Identifiers */\r
{\r
/* Only Standard-Ids are accepted, Set Mask */\r
+ // HalCoGen\r
CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
/* Message valid, Id, Direction */\r
CanRegs[Controller]->IFx[IfRegId].ARB = 0x80000000 | ((hoh->CanIdValue & 0x7FF) << 18) | hoh->CanObjectType;\r
else if(hoh->CanIdType == CAN_ID_TYPE_EXTENDED) /* Extended Identifiers */\r
{\r
/* Only Extended-Ids are accepted, Set Mask */\r
- CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0xC0000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF); // HalCoGen\r
+ // C = bit 30: The message direction bit (Dir) is used for acceptance filtering.\r
+ // CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
/* Message valid, Id, Direction */\r
CanRegs[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFFF) | hoh->CanObjectType;\r
}\r
/* Set Bit Timing Register */\r
CanRegs[Controller]->BTR = Can_CalculateBTR(Controller);\r
\r
- /* Reset CCE Bit */\r
+ /* Reset CCE Bit, i.e. disable configuration change */\r
CanRegs[Controller]->CTL &= ~0x00000040;\r
\r
#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
\r
DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
\r
- /* Read actual MaskRegister value of MessageObject */\r
+ /* Read actual MaskRegister value of MessageObject; TxRqst/NewDat */\r
CanRegs[Controller]->IFx[IfRegId].COM = 0x004C0000 | (MsgNr);\r
\r
DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
/* Set new Mask */\r
CanRegs[Controller]->IFx[IfRegId].MASK |= (*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF;\r
/* Write new Mask to MaskRegister */\r
- CanRegs[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr);\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr); // E8??\r
\r
IfRegId ^= 1;\r
}\r
break;\r
\r
case CAN_T_SLEEP:\r
- /* Set PDR Bit */\r
+ /* Set PDR Bit - Local Power Down Mode requested */\r
CanRegs[Controller]->CTL |= 0x01000000;\r
/* Save actual Register status */\r
RegBuf = CanRegs[Controller]->CTL;\r
uint8 *CurTxRqstPtr;\r
imask_t state;\r
\r
- CurSduPtr = PduInfo->sdu;\r
+ CurSduPtr = PduInfo->sdu; // e.g. ComArcIPduBuffer_TX_PDU\r
\r
\r
/* DET Error Check */\r
continue; // This message object is not part of this hoh.\r
}\r
/* Check if TxRqst Bit of MsgObject is set */\r
- if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
+ if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F))) // (1 << (MsgNr & 0x1F)) - bitIndex\r
{\r
continue;\r
}\r
#include <string.h>\r
#include "../kernel/core_cr4.h"\r
\r
-GIO_RegisterType *GPIO_ports[] = { GIO_PORTA_BASE, GIO_PORTB_BASE, GIO_HET_PORT1_BASE };\r
+GIO_RegisterType *GPIO_ports[] = { GIO_PORTA_BASE, GIO_PORTB_BASE, GIO_HET_PORT1_BASE, GIO_DMM_PORT_BASE };\r
\r
#define DIO_GET_PORT_FROM_CHANNEL_ID(_channelId) (_channelId >> 8)\r
#define DIO_GET_BIT_FROM_CHANNEL_ID(_channelId) (1 << (_channelId & 0x1F))\r
{\r
VALIDATE_PORT(portId, DIO_WRITEPORT_ID);\r
\r
- GPIO_ports[portId]->DOUT = (uint32)level;\r
+ GPIO_ports[portId]->DOUT = (uint16)level; // uint32 for TMS570LS3137HDK, uint16 for RPP\r
\r
#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
cleanup:\r
\r
#define PORT_NOT_CONFIGURED 0x00000000\r
\r
-#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30)\r
-#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50)\r
+#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30) // GIO Port A\r
+#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50) // GIO Port B\r
#define PORT_2_BASE ((Port_RegisterType *)0xFFF7B848) // N2HET1 Base\r
-#define PORT_3_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_3_BASE ((Port_RegisterType *)0xFFFFF76C) // DMM used as a GIO\r
#define PORT_4_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_5_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_6_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#endif\r
\r
void Port_RefreshPin(uint16 pinNumber) {\r
- uint8 port = GET_PIN_PORT(_configPtr->pins[pinNumber].pin);\r
+ uint32 port = GET_PIN_PORT(_configPtr->pins[pinNumber].pin);\r
uint32 mask = GET_PIN_MASK(_configPtr->pins[pinNumber].pin);\r
- uint16 conf = _configPtr->pins[pinNumber].conf;\r
+ uint32 conf = _configPtr->pins[pinNumber].conf;\r
\r
uint32 pinmux = _configPtr->pins[pinNumber].pinmux;\r
uint8 pinmuxFunctionNum = _configPtr->pins[pinNumber].pinmuxFunctionNum;\r
}\r
\r
\r
-void Port_Init(const Port_ConfigType *configType) {\r
+void Port_Init(const Port_ConfigType *configType) { // note: HalCoGen: gioInit\r
VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);\r
\r
_configPtr = (Port_ConfigType *)configType;\r
for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
Port_RefreshPin(i);\r
}\r
+ if (DMM_USED) {\r
+ for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
+ Dmm_Init(i);\r
+ }\r
+ }\r
\r
_portState = PORT_INITIALIZED;\r
\r
return;\r
}\r
\r
+void Dmm_Init(uint16 pinNumber) {\r
+\r
+ dmmReg->GLBCTRL= 0x00000605; /* DMM switched ON, set 32 bit length */\r
+ //dmmReg->GLBCTRL = 0x5; // don't use DMM_Reset\r
+\r
+ uint32 port = GET_PIN_PORT(_configPtr->pins[pinNumber].pin);\r
+ uint32 mask = GET_PIN_MASK(_configPtr->pins[pinNumber].pin);\r
+\r
+ Port_Base[port]->FUN |= ~mask; // pin usage: 1 - functional, 0 - GIO\r
+ //Port_Base[port]->FUN = 0x00000000;\r
+ //Port_Base[port]->DIR = 0x00000001;\r
+ Port_Base[port]->DIR = 0x7FFFF; // I/O selection: 0 - input, 1 - output (not necessary but assures that all DMM GIO pins are used as outputs in our example)\r
+ Port_Base[port]->PSL &= ~mask; // pull-up/pull-down selection: 0 - pull-down, 1 - pull-up\r
+}\r
+\r
+void Dmm_Reset(const Port_ConfigType *configType) {\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);\r
+\r
+ _configPtr = (Port_ConfigType *)configType;\r
+\r
+ uint32 mask = GET_PIN_MASK(_configPtr->pins[0].pin);\r
+ dmmReg->GLBCTRL |= mask;\r
+ dmmReg->GLBCTRL &= ~mask;\r
+}\r
+\r
#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
{\r
{\r
uint32 CTL;\r
uint32 SR;\r
- unsigned : 16;\r
- unsigned REC : 8;\r
- unsigned TEC : 8;\r
+ unsigned : 16; /* bits 31-16 - Reserved; 0x0008 - Error Counter Register */\r
+ unsigned REC : 8; /* bits 15-8 - Receive Error Counter; 0x0008 - Error Counter Register */\r
+ unsigned TEC : 8; /* bits 7-0 - Transmit Error Counter; 0x0008 - Error Counter Register */\r
uint32 BTR;\r
uint32 IR;\r
uint32 TR;\r
unsigned : 32;\r
struct\r
{\r
- uint32 COM;\r
+ uint32 COM; /* 0x0100: IF1 Command Register - Reserved, Command, Status, Msg Number */\r
uint32 MASK;\r
uint32 ARB;\r
uint32 MC;\r
unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
} GIO_RegisterType;\r
\r
+/** @def GIO_PORTA_BASE\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
#define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)\r
+/** @def GIO_PORTB_BASE\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
#define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)\r
#define GIO_HET_PORT1_BASE ((GIO_RegisterType *)0xFFF7B84CU)\r
\r
*/\r
#define gioREG ((GIO_Base_RegisterType *)0xFFF7BC00U)\r
\r
-/** @def gioPORTA\r
-* @brief GIO Port (A) Register Pointer\r
+\r
+/** @struct dmmBase\r
+* @brief DMM Base Register Definition\r
*\r
-* Pointer used by the GIO driver to access PORTA\r
+* This structure is used to access the DMM module egisters.\r
*/\r
-#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)\r
-\r
-/** @def gioPORTB\r
-* @brief GIO Port (B) Register Pointer\r
+/** @typedef dmmBASE_t\r
+* @brief DMM Register Frame Type Definition\r
*\r
-* Pointer used by the GIO driver to access PORTB\r
+* This type is used to access the DMM Registers.\r
*/\r
-#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)\r
\r
+typedef volatile struct dmmBase\r
+{\r
+ unsigned GLBCTRL; /**< 0x0000: Global control register 0 */\r
+ unsigned INTSET; /**< 0x0004: DMM Interrupt Set Register */\r
+ unsigned INTCLR; /**< 0x0008: DMM Interrupt Clear Register */\r
+ unsigned INTLVL; /**< 0x000C: DMM Interrupt Level Register */\r
+ unsigned INTFLG; /**< 0x0010: DMM Interrupt Flag Register */\r
+ unsigned OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */\r
+ unsigned OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */\r
+ unsigned DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */\r
+ unsigned DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */\r
+ unsigned DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */\r
+ unsigned INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */\r
+ unsigned DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */\r
+ unsigned DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */\r
+ unsigned DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */\r
+ unsigned DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */\r
+ unsigned DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */\r
+ unsigned DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */\r
+ unsigned DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */\r
+ unsigned DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */\r
+ unsigned DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */\r
+ unsigned DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */\r
+ unsigned DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */\r
+ unsigned DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */\r
+ unsigned DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */\r
+ unsigned DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */\r
+ unsigned DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */\r
+ unsigned DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */\r
+ unsigned PC0; /**< 0x006C: DMM Pin Control 0 */\r
+ unsigned PC1; /**< 0x0070: DMM Pin Control 1 */\r
+ unsigned PC2; /**< 0x0074: DMM Pin Control 2 */\r
+ unsigned PC3; /**< 0x0078: DMM Pin Control 3 */\r
+ unsigned PC4; /**< 0x007C: DMM Pin Control 4 */\r
+ unsigned PC5; /**< 0x0080: DMM Pin Control 5 */\r
+ unsigned PC6; /**< 0x0084: DMM Pin Control 6 */\r
+ unsigned PC7; /**< 0x0088: DMM Pin Control 7 */\r
+ unsigned PC8; /**< 0x008C: DMM Pin Control 8 */\r
+} DMM_Base_RegisterType;\r
+\r
+#define dmmReg ((DMM_Base_RegisterType *)0xFFFFF700U)\r
+\r
+#define GIO_DMM_PORT_BASE ((GIO_RegisterType *)0xFFFFF770U)\r
\r
typedef struct\r
{\r
};\r
const ComSignal_type * const ComIPduSignalRefs_RX_PDU[] = {\r
&ComSignal[ Arg1 ],\r
- &ComSignal[ Arg2 ], \r
+ &ComSignal[ Arg2 ],\r
+ /* &ComSignal [ H ],\r
+ * &ComSignal [ E ],\r
+ * &ComSignal [ R ],\r
+ * &ComSignal [ C ],\r
+ * &ComSignal [ U ],\r
+ * &ComSignal [ L ],\r
+ * &ComSignal [ E ],\r
+ * &ComSignal [ S ],\r
+ */\r
NULL,\r
};\r
const ComSignal_type * const ComIPduSignalRefs_TX_PDU[] = {\r
- &ComSignal[ ResultSig ], \r
+ &ComSignal[ ResultSig ],\r
+ /* &ComSignal [ H ],\r
+ * &ComSignal [ E ],\r
+ * &ComSignal [ R ],\r
+ * &ComSignal [ C ],\r
+ * &ComSignal [ U ],\r
+ * &ComSignal [ L ],\r
+ * &ComSignal [ E ],\r
+ * &ComSignal [ S ],\r
+ */\r
NULL,\r
};\r
\r
}\r
\r
void MainTask( void ) {\r
- Com_MainFunctionTx(); // Com_MainFunctionRx();\r
- Com_MainFunctionRx(); // Com_MainFunctionTx();\r
+ Com_MainFunctionRx();\r
+ Com_MainFunctionTx();\r
TerminateTask();\r
}\r
\r
extern const Can_ControllerConfigType CanControllerConfigData[];\r
extern const Can_ConfigSetType CanConfigSetData;\r
\r
-\r
-\r
-\r
// Contains the mapping from CanIf-specific Channels to Can Controllers\r
const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {\r
DCAN1, // Channel_1\r
{\r
{ \r
.CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CANIF_Channel_1, // Transmit: DCAN1\r
+ .CanIfCanControllerIdRef = CANIF_Channel_2, // Transmit to DCAN2\r
.CanIfHthIdSymRef = TxHwObject,\r
.CanIf_Arc_EOL = 1,\r
},\r
{\r
.CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE,\r
- .CanIfCanControllerHrhIdRef = CANIF_Channel_2, // Receive: DCAN2\r
+ .CanIfCanControllerHrhIdRef = CANIF_Channel_1, // Receive to DCAN1\r
.CanIfHrhIdSymRef = RxHwObject,\r
.CanIf_Arc_EOL = 1,\r
},\r
const CanIf_TxPduConfigType CanIfTxPduConfigData[] = {\r
{\r
.CanIfTxPduId = PDUR_REVERSE_PDU_ID_TX_PDU, // Transmit I-PDU; Reverse = PDUR -----> CANIF\r
- .CanIfCanTxPduIdCanId = 1, // 2\r
+ .CanIfCanTxPduIdCanId = 2, // 1\r
.CanIfCanTxPduIdDlc = 8,\r
.CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
.CanIfReadTxPduNotifyStatus = false,\r
#endif\r
- .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_11, // 11 == BASIC CAN\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, // 11 == BASIC CAN, 29 == EXTENDED CAN\r
.CanIfUserTxConfirmation = PduR_CanIfTxConfirmation,\r
.CanIfCanTxPduHthRef = &CanIfHthConfigData_Hoh[0],\r
.PduIdRef = NULL,\r
},\r
{\r
.CanIfTxPduId = PDUR_REVERSE_PDU_ID_FreqInd,\r
- .CanIfCanTxPduIdCanId = 256, // 258\r
+ .CanIfCanTxPduIdCanId = 258, // 256\r
.CanIfCanTxPduIdDlc = 8,\r
.CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
.CanIfReadTxPduNotifyStatus = false,\r
#endif\r
- .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = PduR_CanIfTxConfirmation,\r
.CanIfCanTxPduHthRef = &CanIfHthConfigData_Hoh[0],\r
.PduIdRef = NULL,\r
const CanIf_RxPduConfigType CanIfRxPduConfigData[] = {\r
{\r
.CanIfCanRxPduId = PDUR_PDU_ID_RX_PDU, // Receive I-PDU; CANIF -----> PDUR\r
- .CanIfCanRxPduCanId = 2, // 1\r
+ .CanIfCanRxPduCanId = 1, // 2\r
.CanIfCanRxPduDlc = 8,\r
#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
.CanIfReadRxPduData = false,\r
#endif\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // upper layer\r
.CanIfCanRxPduHrhRef = &CanIfHrhConfigData_Hoh[1], // [0] ??\r
- .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, // CANIF_CAN_ID_TYPE_11\r
.CanIfUserRxIndication = NULL,\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK,\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
},\r
{\r
.CanIfCanRxPduId = PDUR_PDU_ID_FreqReq,\r
- .CanIfCanRxPduCanId = 258, // 256\r
+ .CanIfCanRxPduCanId = 256, // 258\r
.CanIfCanRxPduDlc = 8,\r
#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
.CanIfReadRxPduData = false,\r
#endif\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR,\r
.CanIfCanRxPduHrhRef = &CanIfHrhConfigData_Hoh[1], // [0] ??\r
- .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_11,\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, // CANIF_CAN_ID_TYPE_11\r
.CanIfUserRxIndication = NULL,\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK,\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
const CanIf_InitConfigType CanIfInitConfig =\r
{\r
.CanIfConfigSet = 0, // Not used \r
- .CanIfNumberOfCanRxPduIds = 2, // 1\r
- .CanIfNumberOfCanTXPduIds = 2, // 1\r
+ .CanIfNumberOfCanRxPduIds = 1, // 2\r
+ .CanIfNumberOfCanTXPduIds = 1, // 2\r
.CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
\r
// Containers\r
#define CAN_CFG_H_\r
\r
// Number of controller configs\r
-#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+#define CAN_ARC_CTRL_CONFIG_CNT 2\r
\r
#define CAN_DEV_ERROR_DETECT STD_OFF\r
#define CAN_VERSION_INFO_API STD_OFF\r
\r
\r
//Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_FilterMask = 0x0;\r
-Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_FilterMask = 0x400007FF;\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_FilterMask = 0x000007FF;\r
// Can_FilterMaskType Can_FilterMaskConfigData_FULLMask = 0x1FFFFFFF;\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
- {\r
- .CanObjectId = TxHwObject,\r
- .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
- .CanIdType = CAN_ID_TYPE_STANDARD,\r
- .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
- .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_FilterMask,\r
-\r
- .Can_Arc_MbMask = 0x2,\r
- .Can_Arc_EOL = 1,\r
- },\r
- {\r
+/* {\r
.CanObjectId = RxHwObject,\r
.CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
- .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED, // re-defined from CAN_ID_TYPE_STANDARD\r
+ .CanIdValue = 0x00000001,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
- .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_FilterMask,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_FilterMask,\r
\r
.Can_Arc_MbMask = 0x1,\r
.Can_Arc_EOL = 0,\r
- }\r
-};\r
-\r
-const Can_HardwareObjectType CanHardwareObjectConfig_Controller_2[] = {\r
+ },*/\r
{\r
.CanObjectId = TxHwObject,\r
.CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
- .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanIdValue = 0x00000001,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
- .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_FilterMask,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_FilterMask,\r
\r
- .Can_Arc_MbMask = 0x2,\r
+ .Can_Arc_MbMask = 0x1,\r
.Can_Arc_EOL = 1,\r
- },\r
+ }\r
+};\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_2[] = {\r
{\r
.CanObjectId = RxHwObject,\r
.CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
- .CanIdType = CAN_ID_TYPE_STANDARD,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanIdValue = 0x00000001,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
- .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_FilterMask,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_FilterMask,\r
\r
.Can_Arc_MbMask = 0x1,\r
.Can_Arc_EOL = 0,\r
- }\r
+ },\r
+/* {\r
+ .CanObjectId = TxHwObject,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanIdValue = 0x00000001,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_FilterMask,\r
+\r
+ .Can_Arc_MbMask = 0x2,\r
+ .Can_Arc_EOL = 1,\r
+ }*/\r
};\r
\r
const Can_ControllerConfigType CanControllerConfigData[] =\r
.CanControllerPropSeg = 5, // for calculation see TMS570LS31x tech.ref.manual pg.1169\r
.CanControllerSeg1 = 3,\r
.CanControllerSeg2 = 3,\r
- .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT, // try to switch all to: CAN_ARC_PROCESS_TYPE_POLLING\r
.CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_DCAN1,\r
.Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
- .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Loopback = FALSE, // 0\r
.Can_Arc_Fifo = 0,\r
},\r
{\r
.CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_DCAN2,\r
- .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_2[1],\r
- .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_2[0],\r
+ .Can_Arc_Loopback = FALSE, // 0\r
.Can_Arc_Fifo = 0,\r
}\r
};\r
const uint8 Com_SignalInitValue_ResultSig = 0;\r
const uint8 Com_SignalInitValue_Arg2 = 3;\r
const uint32 Com_SignalInitValue_FreqIndSig = 0;\r
-//const uint32 Com_SignalInitValue_FreqReqSig = 500;\r
-const uint32 Com_SignalInitValue_FreqReqSig = 0x42524548;\r
+const uint32 Com_SignalInitValue_FreqReqSig = 500;\r
+//const uint32 Com_SignalInitValue_FreqReqSig = 0x42524548;\r
\r
//const uint8 Com_SignalInitValue_TxData[9] = {'H','E','R','C','U','L','E','S','\0'};\r
//const uint8 Com_SignalInitValue_RxData[9] = {0};\r
},\r
{\r
.ComHandleId = FreqIndSig,\r
- .ComIPduHandleId = 1, // 0\r
+ .ComIPduHandleId = 0, // 1\r
.Com_Arc_ShadowBuffer = NULL,\r
.ComFirstTimeoutFactor = 0,\r
.ComNotification = NULL,\r
},\r
{\r
.ComHandleId = FreqReqSig,\r
- .ComIPduHandleId = 0, // 1\r
+ .ComIPduHandleId = 1, // 0\r
.Com_Arc_ShadowBuffer = NULL,\r
.ComFirstTimeoutFactor = 0,\r
.ComNotification = Rte_COMCbk_FreqReqSig,\r
Com_Arc_IPdu_type Com_Arc_IPdu[] = {\r
{ // FreqInd\r
.Com_Arc_TxIPduTimers = {\r
- .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0, // 1\r
.ComTxModeRepetitionPeriodTimer = 0,\r
.ComTxIPduMinimumDelayTimer = 0,\r
.ComTxModeTimePeriodTimer = 0\r
},\r
- .Com_Arc_IpduStarted = 0\r
+ .Com_Arc_IpduStarted = 0 // 1\r
},\r
{ // FreqReq\r
.Com_Arc_TxIPduTimers = {\r
},\r
{ // TX_PDU\r
.Com_Arc_TxIPduTimers = {\r
- .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxIPduNumberOfRepetitionsLeft = 1,\r
.ComTxModeRepetitionPeriodTimer = 0,\r
.ComTxIPduMinimumDelayTimer = 0,\r
.ComTxModeTimePeriodTimer = 0\r
},\r
- .Com_Arc_IpduStarted = 0\r
+ .Com_Arc_IpduStarted = 1\r
},\r
};\r
\r
.pinmuxFunctionNum = PINMUX_BALL_ALTERNATE2,\r
.pinmuxBaseNum = 0,\r
},\r
- { // TODO: add configuration\r
+ {\r
.pin = PORT_PIN_DCAN1_TX,\r
.conf = ( PORT_PIN_OUT | PORT_FUNC | PORT_PULL_NONE ),\r
},\r
{\r
.pin = PORT_PIN_DCAN1_RX,\r
.conf = ( PORT_PIN_IN | 0 | PORT_PULL_NONE ),\r
+ },\r
+ {\r
+ .pin = PORT_PIN_DCAN2_TX,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC | PORT_PULL_NONE ),\r
+ },\r
+ {\r
+ .pin = PORT_PIN_DCAN2_RX,\r
+ .conf = ( PORT_PIN_IN | 0 | PORT_PULL_NONE ),\r
}\r
}\r
};\r
/** Allow Pin mode changes during runtime */\r
#define PORT_SET_PIN_MODE_API STD_ON\r
\r
-#define PORT_NUMBER_OF_PINS 3\r
+#define PORT_NUMBER_OF_PINS 5\r
\r
#define PORT_FUNC_NO (0 << 1)\r
#define PORT_FUNC (1 << 1)\r
#define PORT_PULL_DOWN (0 << 3)\r
#define PORT_ODE_ENABLE (1 << 4)\r
#define PORT_DIRECTION_CHANGEABLE (1 << 5)\r
+#define DMM_USED 0\r
\r
/** pins on the base PINMUX0 */\r
/* TODO: add all remaining bases */\r
{ // TODO: check if correct\r
PORT_PIN_DCAN1_TX = 0x0800,\r
PORT_PIN_DCAN1_RX = 0x0801,\r
+ PORT_PIN_DCAN2_TX = 0x0900,\r
+ PORT_PIN_DCAN2_RX = 0x0901,\r
PORT_PIN_LED1 = 0x021b,\r
} Port_PinType;\r
\r
\r
canPdu.length = PduInfoPtr->SduLength;\r
canPdu.sdu = PduInfoPtr->SduDataPtr;\r
- canPdu.swPduHandle = CanTxPduId;\r
+ canPdu.swPduHandle = CanTxPduId; // e.g. ARC_PDUR_CANIF\r
\r
Can_ReturnType rVal = Can_Write(txEntry->CanIfCanTxPduHthRef->CanIfHthIdSymRef, &canPdu);\r
\r
#define PORT_SET_PIN_MODE_ID 0x04
//@}
+/** @name DMM defines */
+#define DMM_SYNC 0
+#define DMM_CLK 1
+#define DMM_DATA0 2
+#define DMM_DATA1 3
+#define DMM_DATA2 4
+#define DMM_DATA3 5
+#define DMM_DATA4 6
+#define DMM_DATA5 7
+#define DMM_DATA6 8
+#define DMM_DATA7 9
+#define DMM_DATA8 10
+#define DMM_DATA9 11
+#define DMM_DATA10 12
+#define DMM_DATA11 13
+#define DMM_DATA12 14
+#define DMM_DATA13 15
+#define DMM_DATA14 16
+#define DMM_DATA15 17
+#define DMM_ENA 18
+
/** @req PORT046
* The type Port_PinDirectionType is a type for defining the direction of a Port Pin.
* PORT_PIN_IN Sets port pin as input.
void Port_Init(const Port_ConfigType *configType);
+void Dmm_Init(uint16 pinNumber); // Dmm will be used as a GIO
+void Dmm_Reset(const Port_ConfigType *configType);
+
#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )
void Port_SetPinDirection(Port_PinType pin, Port_PinDirectionType direction);
#endif
#if defined(USE_PORT)\r
// Setup Port\r
Port_Init(ConfigPtr->PortConfig);\r
+ //Dmm_Reset(ConfigPtr->PortConfig);\r
#endif\r
\r
\r
projects / arc.git / commitdiff