void Adc_DeInit ()\r
{\r
volatile struct ADC_tag *hwPtr;\r
+ boolean okToClear = TRUE;\r
\r
for (int configId = 0; configId < ADC_ARC_CTRL_CONFIG_CNT; configId++) {\r
hwPtr = GET_HW_CONTROLLER(AdcGlobalConfigPtr[configId].hwConfigPtr->hwUnitId);\r
for(Adc_GroupType group = (Adc_GroupType)0; group < AdcConfigPtr->nbrOfGroups; group++)\r
{\r
/* Set group status to idle. */\r
- AdcConfigPtr->groupConfigPtr[group/NOF_GROUP_PER_CONTROLLER/NOF_GROUP_PER_CONTROLLER].status->groupStatus = ADC_IDLE;\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
}\r
\r
/* Disable DMA transfer*/\r
/* Disable all interrupt*/\r
hwPtr->IMR.R = 0;\r
}\r
+ else\r
+ {\r
+ /* Not ok to change adcState if any unit is running */\r
+ okToClear = FALSE;\r
+ }\r
}\r
- /* Clean internal status. */\r
- AdcGlobalConfigPtr = (Adc_ConfigType *)NULL;\r
- adcState = ADC_UNINIT;\r
+\r
+ if(okToClear)\r
+ {\r
+ /* Clean internal status. */\r
+ AdcGlobalConfigPtr = (Adc_ConfigType *)NULL;\r
+ adcState = ADC_UNINIT;\r
+ }\r
}\r
#endif\r
\r
/* Check for development errors. */\r
if (E_OK == Adc_CheckSetupResultBuffer (adcState, AdcConfigPtr, group))\r
{\r
- AdcConfigPtr->groupConfigPtr[group/NOF_GROUP_PER_CONTROLLER/NOF_GROUP_PER_CONTROLLER].status->resultBufferPtr = bufferPtr;\r
+ AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->resultBufferPtr = bufferPtr;\r
\r
returnValue = E_OK;\r
}\r
// Check which group is busy, only one is allowed to be busy at a time in a hw unit\r
for (int group = 0; group < ADC_NBR_OF_GROUPS; group++)\r
{\r
- if((AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus == ADC_BUSY) ||\r
- (AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->groupStatus == ADC_COMPLETED))\r
+ if((AdcConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_BUSY) ||\r
+ (AdcConfigPtr->groupConfigPtr[group].status->groupStatus == ADC_COMPLETED))\r
{\r
#if !defined (ADC_USES_DMA)\r
/* Copy to result buffer */\r
- for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].numberOfChannels; index++)\r
+ for(uint8 index=0; index < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; index++)\r
{\r
#if defined(CFG_MPC5606S)\r
- AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->currResultBufPtr[index] = hwPtr->CDR[32+AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].channelList[index]].B.CDATA;\r
+ AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = hwPtr->CDR[32+AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
#else\r
- AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].status->currResultBufPtr[index] = hwPtr->CDR[AdcConfigPtr->groupConfigPtr[group%NOF_GROUP_PER_CONTROLLER].channelList[index]].B.CDATA;\r
+ AdcConfigPtr->groupConfigPtr[group].status->currResultBufPtr[index] = hwPtr->CDR[AdcConfigPtr->groupConfigPtr[group].channelList[index]].B.CDATA;\r
#endif\r
}\r
#endif\r
GPT_ISR( 8 )\r
#endif\r
#endif\r
+#endif\r
\r
#if defined(CFG_MPC560X)\r
#if defined(CFG_MPC5606S)\r
vuint32_t AWUM:1;\r
vuint32_t MBL:4;\r
vuint32_t BF:1;\r
- vuint32_t SFTM:1;\r
+ vuint32_t SLFM:1;\r
vuint32_t LBKM:1;\r
vuint32_t MME:1;\r
vuint32_t SBDT:1;\r
vuint32_t MDIS:1;\r
vuint32_t FRZ:1;\r
} B;\r
- } PITMCR;\r
+ } MCR;\r
\r
vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */\r
\r
} PSR[234]; \r
\r
}; /* end of INTC_tag */\r
+\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+#include "ip_dspi.h"\r
+\r
+#if 0\r
/****************************************************************************/\r
/* MODULE : DSPI */\r
/* Base Addresses: */\r
} B;\r
} RXFR[4];\r
}; /* end of DSPI_tag */\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+#include "ip_flexcan.h"\r
+\r
+#if 0\r
/****************************************************************************/\r
/* MODULE : FlexCAN */\r
/* Base Addresses: */\r
} RXIMR[64];\r
\r
}; /* end of FLEXCAN_tag */\r
+\r
+#endif\r
+\r
/****************************************************************************/\r
/* MODULE : DMAMUX (base address - 0xFFFD_C000) */\r
/****************************************************************************/\r
case PERIPHERAL_CLOCK_DSPI_B:\r
case PERIPHERAL_CLOCK_DSPI_C:\r
case PERIPHERAL_CLOCK_DSPI_D:\r
+ case PERIPHERAL_CLOCK_DSPI_E:\r
+ case PERIPHERAL_CLOCK_DSPI_F:\r
#if defined(CFG_MPC5516)\r
prescaler = SIU.SYSCLK.B.LPCLKDIV3;\r
break;\r
static void Spi_Isr_D(void) {\r
Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_D));\r
}\r
+static void Spi_Isr_E(void) {\r
+ Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_E));\r
+}\r
+static void Spi_Isr_F(void) {\r
+ Spi_Isr(GET_SPI_UNIT_PTR(DSPI_CTRL_F));\r
+}\r
/* ----------------------------[public functions]----------------------------*/\r
\r
uint32 Spi_GetJobCnt(void);\r
break;\r
#endif\r
#if (SPI_CONTROLLER_TOTAL_CNT > 4)\r
- case 3:\r
+ case 4:\r
ISR_INSTALL_ISR2("SPI_E",Spi_Isr_E, DSPI_E_ISR_EOQF, 15, 0);\r
break;\r
#endif\r
#if (SPI_CONTROLLER_TOTAL_CNT > 5)\r
- case 3:\r
+ case 5:\r
ISR_INSTALL_ISR2("SPI_F",Spi_Isr_F, DSPI_F_ISR_EOQF, 15, 0);\r
break;\r
#endif\r
\r
PIT_INT4, // 5606-128\r
PIT_INT5, // 5606-129\r
- RESERVED43, // 5606-130\r
- RESERVED44, // 5606-131\r
+ PIT_INT6, // 5606-130\r
+ PIT_INT7, // 5606-131\r
RESERVED45, // 5606-132\r
RESERVED46, // 5606-133\r
RESERVED47, // 5606-134\r
PERIPHERAL_CLOCK_DSPI_B,\r
PERIPHERAL_CLOCK_DSPI_C,\r
PERIPHERAL_CLOCK_DSPI_D,\r
+ PERIPHERAL_CLOCK_DSPI_E,\r
+ PERIPHERAL_CLOCK_DSPI_F,\r
#if defined(CFG_MPC560X)\r
PERIPHERAL_CLOCK_EMIOS_0,\r
PERIPHERAL_CLOCK_EMIOS_1,\r
#include <stdlib.h>\r
\r
\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC5606B)\r
\r
/* TODO: This can actually be read from the flash instead */\r
const FlashType flashInfo[] = {\r
[2].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
[2].sectAddr[4] = 0x100000, /* End, NOT a sector */\r
};\r
-#else if defined(CFG_MPC5606B)\r
-\r
-/* TODO: This can actually be read from the flash instead */\r
-const FlashType flashInfo[] = {\r
- /* NO RWW */\r
-\r
- /* Bank 0, Array 0 (LOW) */\r
- [0].sectCnt = 8,\r
- [0].bankSize = 0x80000,\r
-// [0].bankRange = BANK_RANGE_CODE_LOW,\r
- [0].regBase = 0xC3F88000UL,\r
- [0].sectAddr[0] = 0, /* 0, B0F0, LOW */\r
- [0].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
- [0].sectAddr[1] = 0x08000, /* 1, B0F1, LOW */\r
- [0].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
- [0].sectAddr[2] = 0x0c000, /* 2, B0F2, LOW */\r
- [0].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
- [0].sectAddr[3] = 0x10000, /* 3, B0F3, LOW */\r
- [0].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
- [0].sectAddr[4] = 0x18000, /* 4, B0F4, LOW */\r
- [0].addrSpace[4] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 4,\r
- [0].sectAddr[5] = 0x20000, /* 5, B0F5, LOW */\r
- [0].addrSpace[5] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 5,\r
- [0].sectAddr[6] = 0x40000, /* 6, B0F6, MID */\r
- [0].addrSpace[6] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 0,\r
- [0].sectAddr[7] = 0x60000, /* 7, B0F7, MID */\r
- [0].addrSpace[7] = ADDR_SPACE_SET(ADDR_SPACE_MID) + 1,\r
- [0].sectAddr[8] = 0x80000, /* End, NOT a sector */\r
-\r
- /* Bank 1, Data */\r
- [1].sectCnt = 4,\r
- [1].bankSize = 0x810000 - 0x800000,\r
- [1].regBase = 0xC3F8C000UL,\r
- [1].sectAddr[0] = 0x800000, /* LOW */\r
- [1].addrSpace[0] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 0,\r
- [1].sectAddr[1] = 0x804000, /* LOW */\r
- [1].addrSpace[1] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 1,\r
- [1].sectAddr[2] = 0x808000, /* LOW */\r
- [1].addrSpace[2] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 2,\r
- [1].sectAddr[3] = 0x80c000, /* LOW */\r
- [1].addrSpace[3] = ADDR_SPACE_SET(ADDR_SPACE_LOW) + 3,\r
- [1].sectAddr[4] = 0x810000, /* End, NOT a sector */\r
-};\r
\r
#else\r
#error CPU NOT supported\r
#define FLS_WRITE_TIME 0 /* NO SUPPORT */\r
\r
/* MCU Specific */\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC5606B)\r
\r
#define FLASH_BANK_CNT 3\r
#define FLASH_PAGE_SIZE 8\r