#ifndef _MPC5604B_H_\r
#define _MPC5604B_H_\r
\r
+#include "Compiler.h"\r
#include "typedefs.h"\r
\r
#ifdef __cplusplus\r
/****************************************************************************/\r
/* MODULE : DSPI */\r
/****************************************************************************/\r
- struct DSPI_tag {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t MSTR:1;\r
- vuint32_t CONT_SCKE:1;\r
- vuint32_t DCONF:2;\r
- vuint32_t FRZ:1;\r
- vuint32_t MTFE:1;\r
- vuint32_t PCSSE:1;\r
- vuint32_t ROOE:1;\r
- vuint32_t:2;\r
- vuint32_t PCSIS5:1;\r
- vuint32_t PCSIS4:1;\r
- vuint32_t PCSIS3:1;\r
- vuint32_t PCSIS2:1;\r
- vuint32_t PCSIS1:1;\r
- vuint32_t PCSIS0:1;\r
- vuint32_t DOZE:1;\r
- vuint32_t MDIS:1;\r
- vuint32_t DIS_TXF:1;\r
- vuint32_t DIS_RXF:1;\r
- vuint32_t CLR_TXF:1;\r
- vuint32_t CLR_RXF:1;\r
- vuint32_t SMPL_PT:2;\r
- vuint32_t:7;\r
- vuint32_t HALT:1;\r
- } B;\r
- } MCR; /* Module Configuration Register */\r
-\r
- uint32_t dspi_reserved1;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t TCNT:16;\r
- vuint32_t:16;\r
- } B;\r
- } TCR;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t DBR:1;\r
- vuint32_t FMSZ:4;\r
- vuint32_t CPOL:1;\r
- vuint32_t CPHA:1;\r
- vuint32_t LSBFE:1;\r
- vuint32_t PCSSCK:2;\r
- vuint32_t PASC:2;\r
- vuint32_t PDT:2;\r
- vuint32_t PBR:2;\r
- vuint32_t CSSCK:4;\r
- vuint32_t ASC:4;\r
- vuint32_t DT:4;\r
- vuint32_t BR:4;\r
- } B;\r
- } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t TCF:1;\r
- vuint32_t TXRXS:1;\r
- vuint32_t:1;\r
- vuint32_t EOQF:1;\r
- vuint32_t TFUF:1;\r
- vuint32_t:1;\r
- vuint32_t TFFF:1;\r
- vuint32_t:5;\r
- vuint32_t RFOF:1;\r
- vuint32_t:1;\r
- vuint32_t RFDF:1;\r
- vuint32_t:1;\r
- vuint32_t TXCTR:4;\r
- vuint32_t TXNXTPTR:4;\r
- vuint32_t RXCTR:4;\r
- vuint32_t POPNXTPTR:4;\r
- } B;\r
- } SR; /* Status Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t TCFRE:1;\r
- vuint32_t:2;\r
- vuint32_t EOQFRE:1;\r
- vuint32_t TFUFRE:1;\r
- vuint32_t:1;\r
- vuint32_t TFFFRE:1;\r
- vuint32_t TFFFDIRS:1;\r
- vuint32_t:4;\r
- vuint32_t RFOFRE:1;\r
- vuint32_t:1;\r
- vuint32_t RFDFRE:1;\r
- vuint32_t RFDFDIRS:1;\r
- vuint32_t:16;\r
- } B;\r
- } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t CONT:1;\r
- vuint32_t CTAS:3;\r
- vuint32_t EOQ:1;\r
- vuint32_t CTCNT:1;\r
- vuint32_t:4;\r
- vuint32_t PCS5:1;\r
- vuint32_t PCS4:1;\r
- vuint32_t PCS3:1;\r
- vuint32_t PCS2:1;\r
- vuint32_t PCS1:1;\r
- vuint32_t PCS0:1;\r
- vuint32_t TXDATA:16;\r
- } B;\r
- } PUSHR; /* PUSH TX FIFO Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t RXDATA:16;\r
- } B;\r
- } POPR; /* POP RX FIFO Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t TXCMD:16;\r
- vuint32_t TXDATA:16;\r
- } B;\r
- } TXFR[4]; /* Transmit FIFO Registers */\r
-\r
- vuint32_t DSPI_reserved_txf[12];\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t RXDATA:16;\r
- } B;\r
- } RXFR[4]; /* Transmit FIFO Registers */\r
-\r
- vuint32_t DSPI_reserved_rxf[12];\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t MTOE:1;\r
- vuint32_t:1;\r
- vuint32_t MTOCNT:6;\r
- vuint32_t:4;\r
- vuint32_t TXSS:1;\r
- vuint32_t TPOL:1;\r
- vuint32_t TRRE:1;\r
- vuint32_t CID:1;\r
- vuint32_t DCONT:1;\r
- vuint32_t DSICTAS:3;\r
- vuint32_t:6;\r
- vuint32_t DPCS5:1;\r
- vuint32_t DPCS4:1;\r
- vuint32_t DPCS3:1;\r
- vuint32_t DPCS2:1;\r
- vuint32_t DPCS1:1;\r
- vuint32_t DPCS0:1;\r
- } B;\r
- } DSICR; /* DSI Configuration Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t SER_DATA:16;\r
- } B;\r
- } SDR; /* DSI Serialization Data Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t ASER_DATA:16;\r
- } B;\r
- } ASDR; /* DSI Alternate Serialization Data Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t COMP_DATA:16;\r
- } B;\r
- } COMPR; /* DSI Transmit Comparison Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t DESER_DATA:16;\r
- } B;\r
- } DDR; /* DSI deserialization Data Register */\r
+#include "ip_dspi.h"\r
\r
- }; /* end of DSPI_tag */\r
/****************************************************************************/\r
/* MODULE : ECSM */\r
/****************************************************************************/\r
CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
\r
- SIU.PSMI[0].R = 0x01;\r
+ SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */\r
+ SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */\r
\r
#elif defined(CFG_MPC5606S)\r
// Write pll parameters.\r
//#include <stdio.h>\r
#include "Mcu.h"\r
#include "math.h"\r
+#if (SPI_IMPLEMENTATION==SPI_DMA)\r
#include "Dma.h"\r
+#endif\r
#include "Det.h"\r
#include "isr.h"\r
/* ----------------------------[private define]------------------------------*/\r
\r
/**\r
* Get the buffer for a channel.\r
- *
- * @param ch
- * @param length
- * @return
+ *\r
+ * @param ch\r
+ * @param length\r
+ * @return\r
*/\r
static Spi_DataType *spiGetRxBuf(Spi_ChannelType ch, Spi_NumberOfDataType *length ) {\r
Spi_DataType *buf;\r
\r
#if (SPI_IMPLEMENTATION==SPI_DMA)\r
/**\r
- *
- * @param spiUnit
- * @param jobConfig
- * @return
+ *\r
+ * @param spiUnit\r
+ * @param jobConfig\r
+ * @return\r
*/\r
static void Spi_DoWrite_DMA( Spi_UnitType *spiUnit,Spi_JobType jobIndex,\r
const Spi_JobConfigType *jobConfig )\r
\r
\r
\r
-The Freescale MPC5606S is an PowerPC process with a e200Z0h core, VLE only \r
+The Freescale MPC5604B is an PowerPC process with a e200Z0h core, VLE only \r
\r
Datasheets:\r
Eval board:\r
- http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=XPC560SKIT \r
- http://cache.freescale.com/files/microcontrollers/hardware_tools/schematics/XPC560SADPT176SSCH.pdf?fpsp=1\r
- http://cache.freescale.com/files/32bit/doc/user_guide/XPC560SEVBUM.pdf?fpsp=1\r
- Mainboard schematic\r
- http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC560xB_EVB&parentCode=XPC56xxMB&fpsp=1&nodeId=01624606C1427E\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TRK-MPC5604B\r
\r
- MPC560x\r
- http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC560xS&fsrch=1&sr=1\r
+ MPC560xB\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC560xB&webpageId=121120349534072559427E&nodeId=01624606C1427E&fromPage=tax\r
\r
Board:\r
8Mhz external crystal\r
Code Warrior\r
\r
Info: \r
- MPC5606S\r
+ MPC5604B\r
CPU: e200z0h (VLE only)\r
Freq: 64 Mhz\r
- Flash: 1.0 MB, primary\r
+ Flash: 512KB, primary\r
64K, data flash\r
RAM: 48K, ECC\r
- 160K, Graphics RAM (not ECC)\r
\r
Memory Map:\r
- 0x0000_0000 -> 0x000f_ffff Flash\r
+ 0x0000_0000 -> 0x0007_ffff Flash\r
0x0080_0000 -> 0x0080_ffff Data Flash\r
0x4000_0000 -> 0x4000_bfff SRAM\r
- 0x6000_0000 -> 0x6002_7fff Graphics SRAM\r
\r
\r
\r
-== SPI == \r
-\r
-Adding a SPI EEPROM (Microship 25LC160B)\r
-\r
-To the left are the pins as they are names in XPC56xxMBSCH (schema for the main board, page 11 of 12) \r
-\r
-<- XPC560S ->#<---------------------- MCU ---------------------------------------->\r
- # PAD Func Per # Shared with\r
---------------------------------------------------------------------------------------------\r
-SINB,PJ1-7 # PB[7] 23 1 SIN_0 DSPI_0 56 (SIUL/PWM/Timer)\r
-SOUTB,PJ1-8 # PB[8] 24 1 SOUT_0 DSPI_0 55 (SIUL/PWM/Timer) \r
-SCKB,PJ1-9 # PB[9] 25 1 SCK_0 DSPI_0 54 (SIUL/PWM/Timer) \r
-PCSB2,PJ1-12 # PB[12] 28 3 PCS2_0 DSPI_0 48 (SIUL/LinFlex_1/Timer)\r
-PCSB1,PJ1-11 # PB[13] 29 3 PCS1_0 DSPI_0 49 (SIUL/LinFlex_1/Timer)\r
-PCSB0,PJ1-10 # PH[4] 103 1 PCS0_0 DSPI_0 61 (SIUL/PWM/Timer/Control) Control=CLKOUT\r
-\r
-25LC160B\r
- CS - Connect to PJ1-11\r
- /WP - High\r
- /HOLD - Low\r
- Rest of the pins are obvious\r
- \r
- Connected with 5V logic\r
-\r
-PORT J will have the following layout \r
-(With ArcCore internal harness and SO/SI as seen from memory):\r
-\r
- 1-X X-2\r
- 3-X X-4\r
- 5-X X-6\r
- SO/Brown 7-X X-8 SI/Orange\r
- SCK/Blue 9-X X-10 \r
- CS/Green 11-X X-12\r
- 13-X X-14\r
- 15-X X-16 \r
- Gnd/Black 17-X X-18 VCC/Red \r
-\r
-\r
-\r
\r
\r
\r
+++ /dev/null
-/*\r
-* Configuration of module: Spi (Spi_Cfg.h)\r
-*\r
-* Created by: \r
-* Copyright: \r
-*\r
-* Configured for (MCU): MPC560x\r
-*\r
-* Module vendor: ArcCore\r
-* Generator version: 2.0.13\r
-*\r
-* Generated by Arctic Studio (http://arccore.com) \r
-* on Tue Jun 14 20:57:25 CEST 2011\r
-*/\r
-\r
-
-\r
-#ifndef SPI_CFG_H\r
-#define SPI_CFG_H\r
-\r
-#include "Dma.h"\r
-#include "mpc55xx.h"\r
-#include "Mcu.h"\r
-\r
-#define DSPI_CTRL_A 0\r
-#define DSPI_CTRL_B 1\r
-#define DSPI_CTRL_C 2\r
-#define DSPI_CTRL_D 3\r
-\r
-/*\r
- * General configuration\r
- */\r
-\r
-// Switches the Spi_Cancel function ON or OFF.\r
-#define SPI_CANCEL_API STD_ON\r
-\r
-// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.\r
-// LEVEL 0 - Only Internal buffers\r
-// LEVEL 1 - Only external buffers\r
-// LEVEL 2 - Both internal/external buffers\r
-#define SPI_CHANNEL_BUFFERS_ALLOWED 1\r
-\r
-#define SPI_DEV_ERROR_DETECT STD_ON\r
-// Switches the Spi_GetHWUnitStatus function ON or OFF.\r
-#define SPI_HW_STATUS_API STD_ON\r
-// Switches the Interruptible Sequences handling functionality ON or OFF.\r
-#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF\r
-\r
-// LEVEL 0 - Simple sync\r
-// LEVEL 1 - Basic async\r
-// LEVEL 2 - Enhanced mode\r
-#define SPI_LEVEL_DELIVERED 2\r
-\r
-#define SPI_VERSION_INFO_API STD_ON\r
-\r
-#if 0\r
-#if SPI_LEVEL_DELIVERED>=1\r
-#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON\r
-#endif\r
-#endif\r
-\r
-// External devices\r
-typedef enum {\r
- SPI_device_1,\r
-} Spi_ExternalDeviceTypeType;\r
-\r
-// Channels\r
-#define SPI_CH_WREN 0\r
-#define SPI_CH_CMD 1\r
-#define SPI_CH_DATA 2\r
-#define SPI_CH_ADDR 3\r
-\r
-// Jobs\r
-#define SPI_JOB_CMD2 0 \r
-#define SPI_JOB_DATA 1 \r
-#define SPI_JOB_CMD 2 \r
-#define SPI_JOB_WREN 3 \r
-\r
-// Sequences\r
-#define SPI_SEQ_CMD 0\r
-#define SPI_SEQ_WRITE 1\r
-#define SPI_SEQ_READ 2\r
-#define SPI_SEQ_CMD2 3\r
-\r
-\r
-#define SPI_MAX_JOB 4\r
-#define SPI_MAX_CHANNEL 4\r
-#define SPI_MAX_SEQUENCE 4\r
-\r
-#define SPI_USE_HW_UNIT_0 STD_ON\r
-#define SPI_USE_HW_UNIT_1 STD_OFF\r
-#define SPI_USE_HW_UNIT_2 STD_OFF\r
-#define SPI_USE_HW_UNIT_3 STD_OFF\r
-\r
-\r
-#endif /*SPI_CFG_H*/\r
+++ /dev/null
-/*\r
-* Configuration of module: Spi (Spi_Lcfg.c)\r
-*\r
-* Created by: \r
-* Copyright: \r
-*\r
-* Configured for (MCU): MPC560x\r
-*\r
-* Module vendor: ArcCore\r
-* Generator version: 2.0.13\r
-*\r
-* Generated by Arctic Studio (http://arccore.com) \r
-* on Tue Jun 14 20:57:25 CEST 2011\r
-*/\r
-\r
-\r
-\r
-#include "Spi.h"\r
-#include "Spi_Cfg.h"\r
-#include <stdlib.h>\r
-\r
-\r
-\r
-// SPI_0\r
-//#define SPI_0_CS 1 /* Using PCSB1 */\r
-#define SPI_0_CS 2 /* Using PCSB2 */\r
-\r
-\r
-#define SPI_SEQ_END_NOTIFICATION NULL\r
-#define SPI_JOB_END_NOTIFICAITON NULL\r
-\r
-// Notifications\r
-// Seq\r
-#define SPI_SEQ_CMD_END_NOTIFICATION NULL\r
-#define SPI_SEQ_WRITE_END_NOTIFICATION NULL\r
-#define SPI_SEQ_READ_END_NOTIFICATION NULL\r
-#define SPI_SEQ_CMD2_END_NOTIFICATION NULL\r
-// Jobs\r
-#define SPI_JOB_CMD2_END_NOTIFICATION NULL\r
-#define SPI_JOB_DATA_END_NOTIFICATION NULL\r
-#define SPI_JOB_CMD_END_NOTIFICATION NULL\r
-#define SPI_JOB_WREN_END_NOTIFICATION NULL\r
-\r
-\r
-/*************** Sequences **************/\r
-const Spi_SequenceConfigType SpiSequenceConfigData[] =\r
-{\r
- {\r
- .SpiSequenceId = SPI_SEQ_CMD,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_CMD_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_CMD,\r
- (-1)\r
- },\r
- },\r
- {\r
- .SpiSequenceId = SPI_SEQ_WRITE,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_WRITE_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_WREN,\r
- SPI_JOB_DATA,\r
- (-1)\r
- },\r
- },\r
- {\r
- .SpiSequenceId = SPI_SEQ_READ,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_READ_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_DATA,\r
- (-1)\r
- },\r
- },\r
- {\r
- .SpiSequenceId = SPI_SEQ_CMD2,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_CMD2_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_CMD2,\r
- (-1)\r
- },\r
- },\r
-};\r
-\r
-/*************** Jobs **************/\r
-const Spi_JobConfigType SpiJobConfigData[] =\r
-{\r
- {\r
- .SpiJobId = SPI_JOB_CMD2,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_CMD2_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_CMD,\r
- SPI_CH_DATA,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
- {\r
- .SpiJobId = SPI_JOB_DATA,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_DATA_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_CMD,\r
- SPI_CH_ADDR,\r
- SPI_CH_DATA,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
- {\r
- .SpiJobId = SPI_JOB_CMD,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_CMD_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_CMD,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
- {\r
- .SpiJobId = SPI_JOB_WREN,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_WREN_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_WREN,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
-};\r
-\r
-uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }\r
-\r
-\r
-/*************** Channels **************/\r
-const Spi_ChannelConfigType SpiChannelConfigData[] =\r
-{\r
- {\r
- .SpiChannelId = SPI_CH_WREN,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 8,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 1, \r
- .SpiDefaultData = 6,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = SPI_CH_CMD,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 8,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 64, \r
- .SpiDefaultData = 0,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = SPI_CH_DATA,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 8,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 64, \r
- .SpiDefaultData = 0,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = SPI_CH_ADDR,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 16,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 64, \r
- .SpiDefaultData = 0,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = (-1),\r
- }\r
-};\r
-\r
-uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }\r
-\r
-/*************** External Devices **************/\r
-const Spi_ExternalDeviceType SpiExternalConfigData[] =\r
-{\r
- {\r
- .SpiBaudrate = 100000UL,\r
- .SpiCsIdentifier = 1,\r
- .SpiCsPolarity = STD_LOW,\r
- .SpiDataShiftEdge = SPI_EDGE_LEADING,\r
- .SpiEnableCs = 0, // NOT SUPPORTED IN TOOLS\r
- .SpiShiftClockIdleLevel = STD_LOW,\r
- .SpiTimeClk2Cs = 606, // ns\r
- .SpiTimeCs2Clk = 606, // ns\r
- },\r
-};\r
-\r
-uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }\r
-\r
-\r
-\r
-const Spi_DriverType SpiConfigData =\r
-{\r
- .SpiMaxChannel = SPI_MAX_CHANNEL,\r
- .SpiMaxJob = SPI_MAX_JOB,\r
- .SpiMaxSequence = SPI_MAX_SEQUENCE,\r
- .SpiChannelConfig = &SpiChannelConfigData[0],\r
- .SpiSequenceConfig = &SpiSequenceConfigData[0],\r
- .SpiJobConfig = &SpiJobConfigData[0],\r
- .SpiExternalDevice = &SpiExternalConfigData[0],\r
-};\r
-\r
+++ /dev/null
-/*\r
-* Configuration of module: Spi (Spi_Cfg.h)\r
-*\r
-* Created by: \r
-* Copyright: \r
-*\r
-* Configured for (MCU): MPC560x\r
-*\r
-* Module vendor: ArcCore\r
-* Generator version: 2.0.13\r
-*\r
-* Generated by Arctic Studio (http://arccore.com) \r
-* on Tue Jun 14 20:57:25 CEST 2011\r
-*/\r
-\r
-
-\r
-#ifndef SPI_CFG_H\r
-#define SPI_CFG_H\r
-\r
-#include "Dma.h"\r
-#include "mpc55xx.h"\r
-#include "Mcu.h"\r
-\r
-#define DSPI_CTRL_A 0\r
-#define DSPI_CTRL_B 1\r
-#define DSPI_CTRL_C 2\r
-#define DSPI_CTRL_D 3\r
-\r
-/*\r
- * General configuration\r
- */\r
-\r
-// Switches the Spi_Cancel function ON or OFF.\r
-#define SPI_CANCEL_API STD_ON\r
-\r
-// Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.\r
-// LEVEL 0 - Only Internal buffers\r
-// LEVEL 1 - Only external buffers\r
-// LEVEL 2 - Both internal/external buffers\r
-#define SPI_CHANNEL_BUFFERS_ALLOWED 1\r
-\r
-#define SPI_DEV_ERROR_DETECT STD_ON\r
-// Switches the Spi_GetHWUnitStatus function ON or OFF.\r
-#define SPI_HW_STATUS_API STD_ON\r
-// Switches the Interruptible Sequences handling functionality ON or OFF.\r
-#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_OFF\r
-\r
-// LEVEL 0 - Simple sync\r
-// LEVEL 1 - Basic async\r
-// LEVEL 2 - Enhanced mode\r
-#define SPI_LEVEL_DELIVERED 2\r
-\r
-#define SPI_VERSION_INFO_API STD_ON\r
-\r
-#if 0\r
-#if SPI_LEVEL_DELIVERED>=1\r
-#define SPI_INTERRUPTIBLE_SEQ_ALLOWED STD_ON\r
-#endif\r
-#endif\r
-\r
-// External devices\r
-typedef enum {\r
- SPI_device_1,\r
-} Spi_ExternalDeviceTypeType;\r
-\r
-// Channels\r
-#define SPI_CH_WREN 0\r
-#define SPI_CH_CMD 1\r
-#define SPI_CH_DATA 2\r
-#define SPI_CH_ADDR 3\r
-\r
-// Jobs\r
-#define SPI_JOB_CMD2 0 \r
-#define SPI_JOB_DATA 1 \r
-#define SPI_JOB_CMD 2 \r
-#define SPI_JOB_WREN 3 \r
-\r
-// Sequences\r
-#define SPI_SEQ_CMD 0\r
-#define SPI_SEQ_WRITE 1\r
-#define SPI_SEQ_READ 2\r
-#define SPI_SEQ_CMD2 3\r
-\r
-\r
-#define SPI_MAX_JOB 4\r
-#define SPI_MAX_CHANNEL 4\r
-#define SPI_MAX_SEQUENCE 4\r
-\r
-#define SPI_USE_HW_UNIT_0 STD_ON\r
-#define SPI_USE_HW_UNIT_1 STD_OFF\r
-#define SPI_USE_HW_UNIT_2 STD_OFF\r
-#define SPI_USE_HW_UNIT_3 STD_OFF\r
-\r
-\r
-#endif /*SPI_CFG_H*/\r
+++ /dev/null
-/*\r
-* Configuration of module: Spi (Spi_Lcfg.c)\r
-*\r
-* Created by: \r
-* Copyright: \r
-*\r
-* Configured for (MCU): MPC560x\r
-*\r
-* Module vendor: ArcCore\r
-* Generator version: 2.0.13\r
-*\r
-* Generated by Arctic Studio (http://arccore.com) \r
-* on Tue Jun 14 20:57:25 CEST 2011\r
-*/\r
-\r
-\r
-\r
-#include "Spi.h"\r
-#include "Spi_Cfg.h"\r
-#include <stdlib.h>\r
-\r
-\r
-\r
-// SPI_0\r
-//#define SPI_0_CS 1 /* Using PCSB1 */\r
-#define SPI_0_CS 2 /* Using PCSB2 */\r
-\r
-\r
-#define SPI_SEQ_END_NOTIFICATION NULL\r
-#define SPI_JOB_END_NOTIFICAITON NULL\r
-\r
-// Notifications\r
-// Seq\r
-#define SPI_SEQ_CMD_END_NOTIFICATION NULL\r
-#define SPI_SEQ_WRITE_END_NOTIFICATION NULL\r
-#define SPI_SEQ_READ_END_NOTIFICATION NULL\r
-#define SPI_SEQ_CMD2_END_NOTIFICATION NULL\r
-// Jobs\r
-#define SPI_JOB_CMD2_END_NOTIFICATION NULL\r
-#define SPI_JOB_DATA_END_NOTIFICATION NULL\r
-#define SPI_JOB_CMD_END_NOTIFICATION NULL\r
-#define SPI_JOB_WREN_END_NOTIFICATION NULL\r
-\r
-\r
-/*************** Sequences **************/\r
-const Spi_SequenceConfigType SpiSequenceConfigData[] =\r
-{\r
- {\r
- .SpiSequenceId = SPI_SEQ_CMD,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_CMD_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_CMD,\r
- (-1)\r
- },\r
- },\r
- {\r
- .SpiSequenceId = SPI_SEQ_WRITE,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_WRITE_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_WREN,\r
- SPI_JOB_DATA,\r
- (-1)\r
- },\r
- },\r
- {\r
- .SpiSequenceId = SPI_SEQ_READ,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_READ_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_DATA,\r
- (-1)\r
- },\r
- },\r
- {\r
- .SpiSequenceId = SPI_SEQ_CMD2,\r
- .SpiInterruptibleSequence = false,\r
- .SpiSeqEndNotification = SPI_SEQ_CMD2_END_NOTIFICATION,\r
- .JobAssignment = { \r
- SPI_JOB_CMD2,\r
- (-1)\r
- },\r
- },\r
-};\r
-\r
-/*************** Jobs **************/\r
-const Spi_JobConfigType SpiJobConfigData[] =\r
-{\r
- {\r
- .SpiJobId = SPI_JOB_CMD2,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_CMD2_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_CMD,\r
- SPI_CH_DATA,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
- {\r
- .SpiJobId = SPI_JOB_DATA,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_DATA_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_CMD,\r
- SPI_CH_ADDR,\r
- SPI_CH_DATA,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
- {\r
- .SpiJobId = SPI_JOB_CMD,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_CMD_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_CMD,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
- {\r
- .SpiJobId = SPI_JOB_WREN,\r
- .SpiHwUnit = CSIB0,\r
- .SpiJobPriority = 0,//NOT CONFIGURABLE IN TOOLS\r
- .SpiJobEndNotification = SPI_JOB_WREN_END_NOTIFICATION,\r
- .ChannelAssignment = {\r
- SPI_CH_WREN,\r
- (-1)\r
- },\r
- .DeviceAssignment = SPI_device_1,\r
- },\r
-};\r
-\r
-uint32 Spi_GetJobCnt(void ) { return sizeof(SpiJobConfigData)/sizeof(SpiJobConfigData[0]); }\r
-\r
-\r
-/*************** Channels **************/\r
-const Spi_ChannelConfigType SpiChannelConfigData[] =\r
-{\r
- {\r
- .SpiChannelId = SPI_CH_WREN,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 8,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 1, \r
- .SpiDefaultData = 6,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = SPI_CH_CMD,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 8,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 64, \r
- .SpiDefaultData = 0,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = SPI_CH_DATA,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 8,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 64, \r
- .SpiDefaultData = 0,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = SPI_CH_ADDR,\r
- .SpiChannelType = SPI_EB,\r
- .SpiDataWidth = 16,\r
- .SpiIbNBuffers = 0,\r
- .SpiEbMaxLength = 64, \r
- .SpiDefaultData = 0,\r
- .SpiTransferStart = SPI_TRANSFER_START_MSB,\r
- },\r
- {\r
- .SpiChannelId = (-1),\r
- }\r
-};\r
-\r
-uint32 Spi_GetChanneCnt(void ) { return sizeof(SpiChannelConfigData)/sizeof(SpiChannelConfigData[0]); }\r
-\r
-/*************** External Devices **************/\r
-const Spi_ExternalDeviceType SpiExternalConfigData[] =\r
-{\r
- {\r
- .SpiBaudrate = 100000UL,\r
- .SpiCsIdentifier = 1,\r
- .SpiCsPolarity = STD_LOW,\r
- .SpiDataShiftEdge = SPI_EDGE_LEADING,\r
- .SpiEnableCs = 0, // NOT SUPPORTED IN TOOLS\r
- .SpiShiftClockIdleLevel = STD_LOW,\r
- .SpiTimeClk2Cs = 606, // ns\r
- .SpiTimeCs2Clk = 606, // ns\r
- },\r
-};\r
-\r
-uint32 Spi_GetExternalDeviceCnt(void ) { return sizeof(SpiExternalConfigData)/sizeof(SpiExternalConfigData[0]); }\r
-\r
-\r
-\r
-const Spi_DriverType SpiConfigData =\r
-{\r
- .SpiMaxChannel = SPI_MAX_CHANNEL,\r
- .SpiMaxJob = SPI_MAX_JOB,\r
- .SpiMaxSequence = SPI_MAX_SEQUENCE,\r
- .SpiChannelConfig = &SpiChannelConfigData[0],\r
- .SpiSequenceConfig = &SpiSequenceConfigData[0],\r
- .SpiJobConfig = &SpiJobConfigData[0],\r
- .SpiExternalDevice = &SpiExternalConfigData[0],\r
-};\r
-\r
projects / arc.git / commitdiff