1 /*****************************************************************
\r
3 * FILE : MPC5604B_0M27V_0100.h
\r
5 * DESCRIPTION : This is the header file describing the register
\r
7 * MPC5604B, mask set = 0M27V
\r
8 * SPC560B4, mask set = FB50X20B
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10 * COPYRIGHT :(c) 2009, Freescale & STMicroelectronics
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13 * DATE : 08 MAY 2009
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15 * HISTORY : Original source taken from jdp_0100.h.
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16 * Updated to be compatable with
\r
17 * - MPC5604B Mask ID 0M27V
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18 * - MPC5604B Reference Manual Rev 3 Draft A
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19 * - SPC560B4 Mask ID FB50X20B
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20 * - SPC560B4 Reference Manual Rev 3 Draft A
\r
22 ******************************************************************/
\r
24 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
\r
26 /*****************************************************************
\r
27 * Example instantiation and use:
\r
29 * <MODULE>.<REGISTER>.B.<BIT> = 1;
\r
30 * <MODULE>.<REGISTER>.R = 0x10000000;
\r
32 ******************************************************************/
\r
34 #ifndef _MPC5604B_H_
\r
35 #define _MPC5604B_H_
\r
37 #include "Compiler.h"
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38 #include "typedefs.h"
\r
48 #pragma ANSI_strict off
\r
51 /****************************************************************************/
\r
53 /****************************************************************************/
\r
71 vuint32_t ADCLKSEL:1;
\r
72 vuint32_t ABORTCHAIN:1;
\r
78 } MCR; /* MAIN CONFIGURATION REGISTER */
\r
89 vuint32_t CTUSTART:1;
\r
94 vuint32_t ADCSTATUS:3;
\r
96 } MSR; /* MAIN STATUS REGISTER */
\r
98 int32_t ADC_reserved1[2]; /* (0x010 - 0x008)/4 = 0x02 */
\r
110 } ISR; /* INTERRUPT STATUS REGISTER */
\r
115 vuint32_t EOC_CH31:1;
\r
116 vuint32_t EOC_CH30:1;
\r
117 vuint32_t EOC_CH29:1;
\r
118 vuint32_t EOC_CH28:1;
\r
119 vuint32_t EOC_CH27:1;
\r
120 vuint32_t EOC_CH26:1;
\r
121 vuint32_t EOC_CH25:1;
\r
122 vuint32_t EOC_CH24:1;
\r
123 vuint32_t EOC_CH23:1;
\r
124 vuint32_t EOC_CH22:1;
\r
125 vuint32_t EOC_CH21:1;
\r
126 vuint32_t EOC_CH20:1;
\r
127 vuint32_t EOC_CH19:1;
\r
128 vuint32_t EOC_CH18:1;
\r
129 vuint32_t EOC_CH17:1;
\r
130 vuint32_t EOC_CH16:1;
\r
131 vuint32_t EOC_CH15:1;
\r
132 vuint32_t EOC_CH14:1;
\r
133 vuint32_t EOC_CH13:1;
\r
134 vuint32_t EOC_CH12:1;
\r
135 vuint32_t EOC_CH11:1;
\r
136 vuint32_t EOC_CH10:1;
\r
137 vuint32_t EOC_CH9:1;
\r
138 vuint32_t EOC_CH8:1;
\r
139 vuint32_t EOC_CH7:1;
\r
140 vuint32_t EOC_CH6:1;
\r
141 vuint32_t EOC_CH5:1;
\r
142 vuint32_t EOC_CH4:1;
\r
143 vuint32_t EOC_CH3:1;
\r
144 vuint32_t EOC_CH2:1;
\r
145 vuint32_t EOC_CH1:1;
\r
146 vuint32_t EOC_CH0:1;
\r
148 } CEOCFR[3]; /* Channel Pending Register 0 */
\r
154 vuint32_t MSKEOCTU:1;
\r
155 vuint32_t MSKJEOC:1;
\r
156 vuint32_t MSKJECH:1;
\r
157 vuint32_t MSKEOC:1;
\r
158 vuint32_t MSKECH:1;
\r
160 } IMR; /* INTERRUPT MASK REGISTER */
\r
198 } CIMR[3]; /* Channel Interrupt Mask Register 0 */
\r
213 } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
\r
219 vuint32_t MSKWDG3H:1;
\r
220 vuint32_t MSKWDG2H:1;
\r
221 vuint32_t MSKWDG1H:1;
\r
222 vuint32_t MSKWDG0H:1;
\r
223 vuint32_t MSKWDG3L:1;
\r
224 vuint32_t MSKWDG2L:1;
\r
225 vuint32_t MSKWDG1L:1;
\r
226 vuint32_t MSKWDG0L:1;
\r
228 } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER */
\r
230 int32_t ADC_reserved2[6]; /* (0x050 - 0x038)/4 = 0x06 */
\r
237 vuint32_t THRINV:1;
\r
241 } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */
\r
251 } THRHLR[4]; /* THRESHOLD REGISTER */
\r
253 int32_t ADC_reserved3[4]; /* (0x080 - 0x070)/4 = 0x04 */
\r
259 vuint32_t PREVAL2:2;
\r
260 vuint32_t PREVAL1:2;
\r
261 vuint32_t PREVAL0:2;
\r
262 vuint32_t PRECONV:1;
\r
264 } PSCR; /* PRESAMPLING CONTROL REGISTER */
\r
269 vuint32_t PRES31:1;
\r
270 vuint32_t PRES30:1;
\r
271 vuint32_t PRES29:1;
\r
272 vuint32_t PRES28:1;
\r
273 vuint32_t PRES27:1;
\r
274 vuint32_t PRES26:1;
\r
275 vuint32_t PRES25:1;
\r
276 vuint32_t PRES24:1;
\r
277 vuint32_t PRES23:1;
\r
278 vuint32_t PRES22:1;
\r
279 vuint32_t PRES21:1;
\r
280 vuint32_t PRES20:1;
\r
281 vuint32_t PRES19:1;
\r
282 vuint32_t PRES18:1;
\r
283 vuint32_t PRES17:1;
\r
284 vuint32_t PRES16:1;
\r
285 vuint32_t PRES15:1;
\r
286 vuint32_t PRES14:1;
\r
287 vuint32_t PRES13:1;
\r
288 vuint32_t PRES12:1;
\r
289 vuint32_t PRES11:1;
\r
290 vuint32_t PRES10:1;
\r
302 } PSR[3]; /* PRESAMPLING REGISTER */
\r
304 int32_t ADC_reserved4[1]; /* (0x094 - 0x090)/4 = 0x01 */
\r
310 vuint32_t INPLATCH:1;
\r
312 vuint32_t INPCMP:2;
\r
314 vuint32_t INPSAMP:8;
\r
316 } CTR[3]; /* CONVERSION TIMING REGISTER */
\r
318 int32_t ADC_reserved5[1]; /* (0x0A4 - 0x0A0)/4 = 0x01 */
\r
356 } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER */
\r
358 int32_t ADC_reserved6[1]; /* (0x0B4 - 0x0B0)/4 = 0x01 */
\r
396 } JCMR[3]; /* Injected CONVERSION MASK REGISTER */
\r
398 int32_t ADC_reserved7[1]; /* (0x0C4 - 0x0C0)/4 = 0x01 */
\r
406 } DSDR; /* DECODE SIGNALS DELAY REGISTER */
\r
414 } PDEDR; /* POWER DOWN DELAY REGISTER */
\r
416 int32_t ADC_reserved8[13]; /* (0x100 - 0x0CC)/4 = 0x0D */
\r
424 vuint32_t RESULT:2;
\r
426 vuint32_t CDATA:10;
\r
428 } CDR[96]; /* Channel 0-95 Data REGISTER */
\r
430 }; /* end of ADC_tag */
\r
431 /****************************************************************************/
\r
432 /* MODULE : CANSP */
\r
433 /****************************************************************************/
\r
439 vuint32_t RX_COMPLETE:1;
\r
441 vuint32_t ACTIVE_CK:1;
\r
444 vuint32_t CAN_RX_SEL:3;
\r
446 vuint32_t CAN_SMPLR_EN:1;
\r
448 } CR; /* CANSP Control Register */
\r
452 } SR[12]; /* CANSP Sample Register 0 to 11 */
\r
454 }; /* end of CANSP_tag */
\r
455 /****************************************************************************/
\r
456 /* MODULE : CFLASH */
\r
457 /****************************************************************************/
\r
458 struct CFLASH_tag {
\r
459 union { /* Module Configuration Register */
\r
485 union { /* LML Register */
\r
497 union { /* HBL Register */
\r
502 vuint32_t HBLOCK:8;
\r
506 union { /* SLML Register */
\r
518 union { /* LMS Register */
\r
527 union { /* High Address Space Block Select Register */
\r
535 union { /* Address Register */
\r
544 union { /* CFLASH Configuration Register 0 */
\r
547 vuint32_t BK0_APC:5;
\r
548 vuint32_t BK0_WWSC:5;
\r
549 vuint32_t BK0_RWSC:5;
\r
550 vuint32_t BK0_RWWC2:1;
\r
551 vuint32_t BK0_RWWC1:1;
\r
552 vuint32_t B0_P1_BCFG:2;
\r
553 vuint32_t B0_P1_DPFE:1;
\r
554 vuint32_t B0_P1_IPFE:1;
\r
555 vuint32_t B0_P1_PFLM:2;
\r
556 vuint32_t B0_P1_BFE:1;
\r
557 vuint32_t BK0_RWWC0:1;
\r
558 vuint32_t B0_P0_BCFG:2;
\r
559 vuint32_t B0_P0_DPFE:1;
\r
560 vuint32_t B0_P0_IPFE:1;
\r
561 vuint32_t B0_P0_PFLM:2;
\r
562 vuint32_t B0_P0_BFE:1;
\r
566 union { /* CFLASH Configuration Register 1 */
\r
569 vuint32_t BK1_APC:5;
\r
570 vuint32_t BK1_WWSC:5;
\r
571 vuint32_t BK1_RWSC:5;
\r
572 vuint32_t BK1_RWWC2:1;
\r
573 vuint32_t BK1_RWWC1:1;
\r
575 vuint32_t B0_P1_BFE:1;
\r
576 vuint32_t BK1_RWWC0:1;
\r
578 vuint32_t B1_P0_BFE:1;
\r
582 union { /* cflash Access Protection Register */
\r
606 int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */
\r
608 union { /* User Test Register 0 */
\r
624 union { /* User Test Register 1 */
\r
631 union { /* User Test Register 2 */
\r
638 union { /* User Multiple Input Signature Register 0-4 */
\r
645 }; /* end of CFLASH_tag */
\r
646 /****************************************************************************/
\r
648 /****************************************************************************/
\r
651 /* The CGM provides a unified register interface, enabling access to
\r
655 Base Address | Clock Sources
\r
657 -----------------------------
\r
659 0xC3FE0000 | FXOSC_CTL
\r
661 ---------- | Reserved
\r
663 0xC3FE0040 | SXOSC_CTL
\r
665 0xC3FE0060 | FIRC_CTL
\r
667 0xC3FE0080 | SIRC_CTL
\r
669 0xC3FE00A0 | FMPLL_0
\r
671 ---------- | Reserved
\r
676 /************************************/
\r
677 /* FXOSC_CTL @ CGM base address + 0x0000 */
\r
678 /************************************/
\r
682 vuint32_t OSCBYP:1;
\r
687 vuint32_t OSCDIV:5;
\r
691 } FXOSC_CTL; /* Fast OSC Control Register */
\r
693 /************************************/
\r
694 /* SXOSC_CTL @ CGM base address + 0x0040 */
\r
695 /************************************/
\r
696 int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */
\r
701 vuint32_t OSCBYP:1;
\r
706 vuint32_t OSCDIV:5;
\r
712 } SXOSC_CTL; /* Slow OSC Control Register */
\r
714 /************************************/
\r
715 /* FIRC_CTL @ CGM base address + 0x0060 */
\r
716 /************************************/
\r
717 int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */
\r
723 vuint32_t RCTRIM:6;
\r
728 } FIRC_CTL; /* Fast IRC Control Register */
\r
730 /****************************************/
\r
731 /* SIRC_CTL @ CGM base address + 0x0080 */
\r
732 /****************************************/
\r
733 int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */
\r
739 vuint32_t RCTRIM:5;
\r
743 vuint32_t S_SIRC:1;
\r
745 vuint32_t SIRCON_STDBY:1;
\r
747 } SIRC_CTL; /* Slow IRC Control Register */
\r
749 /*************************************/
\r
750 /* FMPLL @ CGM base address + 0x00A0 */
\r
751 /*************************************/
\r
752 int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */
\r
763 vuint32_t EN_PLL_SW:1;
\r
765 vuint32_t UNLOCK_ONCE:1;
\r
767 vuint32_t I_LOCK:1;
\r
768 vuint32_t S_LOCK:1;
\r
769 vuint32_t PLL_FAIL_MASK:1;
\r
770 vuint32_t PLL_FAIL_FLAG:1;
\r
773 } FMPLL_CR; /* FMPLL Control Register */
\r
778 vuint32_t STRB_BYPASS:1;
\r
780 vuint32_t SPRD_SEL:1;
\r
781 vuint32_t MOD_PERIOD:13;
\r
783 vuint32_t INC_STEP:15;
\r
785 } FMPLL_MR; /* FMPLL Modulation Register */
\r
787 /************************************/
\r
788 /* CMU @ CGM base address + 0x0100 */
\r
789 /************************************/
\r
790 int32_t CGM_reserved5[22]; /* (0x100 - 0x0A8)/4 = 0x16 */
\r
798 vuint32_t CLKSEL1:2;
\r
803 } CMU_CSR; /* Control Status Register */
\r
811 } CMU_FDR; /* Frequency Display Register */
\r
817 vuint32_t HFREF_A:12;
\r
819 } CMU_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
\r
825 vuint32_t LFREF_A:12;
\r
827 } CMU_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
\r
833 vuint32_t FLCI_A:1;
\r
834 vuint32_t FHHI_A:1;
\r
835 vuint32_t FLLI_A:1;
\r
838 } CMU_ISR; /* Interrupt Status Register */
\r
845 } CMU_IMR; /* Interrupt Mask Register */
\r
853 } CMU_MDR; /* Measurement Duration Register */
\r
855 /************************************/
\r
856 /* CGM General Registers @ CGM base address + 0x0370 */
\r
857 /************************************/
\r
858 int32_t CGM_reserved7[149]; /* (0x370 - 0x11C)/4 = 0x95 */
\r
866 } OC_EN; /* Output Clock Enable Register */
\r
872 vuint32_t SELDIV:2;
\r
873 vuint32_t SELCTL:4;
\r
876 } OCDS_SC; /* Output Clock Division Select Register */
\r
882 vuint32_t SELSTAT:4;
\r
885 } SC_SS; /* System Clock Select Status */
\r
894 } SC_DC[3]; /* System Clock Divider Configuration 0->2 */
\r
896 }; /* end of CGM_tag */
\r
897 /****************************************************************************/
\r
899 /****************************************************************************/
\r
905 vuint32_t TRGIEN:1;
\r
909 } CSR; /* Control Status Register */
\r
911 int32_t CTU_reserved0[11]; /* (0x030 - 0x004)/4 = 0x0B */
\r
919 vuint32_t CLR_FLAG:1;
\r
921 vuint32_t CHANNELVALUE:6;
\r
923 } EVTCFGR[64]; /* Event Configuration Register */
\r
925 }; /* end of CTU_tag */
\r
926 /****************************************************************************/
\r
927 /* MODULE : DFLASH */
\r
928 /****************************************************************************/
\r
929 struct DFLASH_tag {
\r
930 union { /* Module Configuration Register */
\r
956 union { /* LML Register */
\r
968 union { /* HBL Register */
\r
973 vuint32_t HBLOCK:8;
\r
977 union { /* SLML Register */
\r
989 union { /* LMS Register */
\r
998 union { /* High Address Space Block Select Register */
\r
1006 union { /* Address Register */
\r
1015 int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */
\r
1017 union { /* User Test Register 0 */
\r
1033 union { /* User Test Register 1 */
\r
1040 union { /* User Test Register 2 */
\r
1047 union { /* User Multiple Input Signature Register 0-4 */
\r
1054 }; /* end of Dflash_tag */
\r
1055 /****************************************************************************/
\r
1056 /* MODULE : DSPI */
\r
1057 /****************************************************************************/
\r
1058 #include "ip_dspi.h"
\r
1060 /****************************************************************************/
\r
1061 /* MODULE : ECSM */
\r
1062 /****************************************************************************/
\r
1067 } PCT; /* ECSM Processor Core Type Register */
\r
1071 } REV; /* ECSM Revision Register */
\r
1073 int32_t ECSM_reserved1;
\r
1077 } IMC; /* ECSM IPS Module Configuration Register */
\r
1079 int8_t ECSM_reserved2[7];
\r
1084 vuint8_t ENBWCR:1;
\r
1086 vuint8_t PRILVL:4;
\r
1088 } MWCR; /* ECSM Miscellaneous Wakeup Control Register */
\r
1090 int32_t ECSM_reserved3[2];
\r
1091 int8_t ECSM_reserved4[3];
\r
1102 } MIR; /* ECSM Miscellaneous Interrupt Register */
\r
1104 int32_t ECSM_reserved5;
\r
1108 } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */
\r
1110 int32_t ECSM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */
\r
1111 int8_t ECSM_reserved7[3];
\r
1123 } ECR; /* ECSM ECC Configuration Register */
\r
1125 int8_t ECSM_reserved8[3];
\r
1137 } ESR; /* ECSM ECC Status Register */
\r
1139 int16_t ECSM_reserved9;
\r
1145 vuint16_t FRC1BI:1;
\r
1146 vuint16_t FR11BI:1;
\r
1148 vuint16_t FRCNCI:1;
\r
1149 vuint16_t FR1NCI:1;
\r
1151 vuint16_t ERRBIT:7;
\r
1153 } EEGR; /* ECSM ECC Error Generation Register */
\r
1155 int32_t ECSM_reserved10;
\r
1159 } FEAR; /* ECSM Flash ECC Address Register */
\r
1161 int16_t ECSM_reserved11;
\r
1169 } FEMR; /* ECSM Flash ECC Master Number Register */
\r
1176 vuint8_t PROTECTION:4;
\r
1178 } FEAT; /* ECSM Flash ECC Attributes Register */
\r
1180 int32_t ECSM_reserved12;
\r
1184 } FEDR; /* ECSM Flash ECC Data Register */
\r
1188 } REAR; /* ECSM RAM ECC Address Register */
\r
1190 int8_t ECSM_reserved13;
\r
1194 } RESR; /* ECSM RAM ECC Address Register */
\r
1202 } REMR; /* ECSM RAM ECC Master Number Register */
\r
1209 vuint8_t PROTECTION:4;
\r
1211 } REAT; /* ECSM RAM ECC Attributes Register */
\r
1213 int32_t ECSM_reserved14;
\r
1217 } REDR; /* ECSM RAM ECC Data Register */
\r
1219 }; /* end of ECSM_tag */
\r
1220 /****************************************************************************/
\r
1221 /* MODULE : EMIOS */
\r
1222 /****************************************************************************/
\r
1223 struct EMIOS_CHANNEL_tag {
\r
1228 vuint32_t CADR:16;
\r
1230 } CADR; /* Channel A Data Register */
\r
1236 vuint32_t CBDR:16;
\r
1238 } CBDR; /* Channel B Data Register */
\r
1244 vuint32_t CCNTR:16;
\r
1246 } CCNTR; /* Channel Counter Register */
\r
1253 vuint32_t ODISSL:2;
\r
1254 vuint32_t UCPRE:2;
\r
1255 vuint32_t UCPEN:1;
\r
1262 vuint32_t FORCMA:1;
\r
1263 vuint32_t FORCMB:1;
\r
1266 vuint32_t EDSEL:1;
\r
1267 vuint32_t EDPOL:1;
\r
1270 } CCR; /* Channel Control Register */
\r
1280 vuint32_t UCOUT:1;
\r
1283 } CSR; /* Channel Status Register */
\r
1286 vuint32_t R; /* Alternate Channel A Data Register */
\r
1289 uint32_t emios_channel_reserved[2];
\r
1291 }; /* end of EMIOS_CHANNEL_tag */
\r
1293 struct EMIOS_tag {
\r
1302 vuint32_t GPREN:1;
\r
1308 } MCR; /* Module Configuration Register */
\r
1339 } GFR; /* Global FLAG Register */
\r
1370 } OUDR; /* Output Update Disable Register */
\r
1376 vuint32_t CHDIS23:1;
\r
1377 vuint32_t CHDIS22:1;
\r
1378 vuint32_t CHDIS21:1;
\r
1379 vuint32_t CHDIS20:1;
\r
1380 vuint32_t CHDIS19:1;
\r
1381 vuint32_t CHDIS18:1;
\r
1382 vuint32_t CHDIS17:1;
\r
1383 vuint32_t CHDIS16:1;
\r
1384 vuint32_t CHDIS15:1;
\r
1385 vuint32_t CHDIS14:1;
\r
1386 vuint32_t CHDIS13:1;
\r
1387 vuint32_t CHDIS12:1;
\r
1388 vuint32_t CHDIS11:1;
\r
1389 vuint32_t CHDIS10:1;
\r
1390 vuint32_t CHDIS9:1;
\r
1391 vuint32_t CHDIS8:1;
\r
1392 vuint32_t CHDIS7:1;
\r
1393 vuint32_t CHDIS6:1;
\r
1394 vuint32_t CHDIS5:1;
\r
1395 vuint32_t CHDIS4:1;
\r
1396 vuint32_t CHDIS3:1;
\r
1397 vuint32_t CHDIS2:1;
\r
1398 vuint32_t CHDIS1:1;
\r
1399 vuint32_t CHDIS0:1;
\r
1401 } UCDIS; /* Disable Channel Register */
\r
1403 uint32_t emios_reserved1[4];
\r
1405 struct EMIOS_CHANNEL_tag CH[28];
\r
1407 }; /* end of EMIOS_tag */
\r
1408 /****************************************************************************/
\r
1409 /* MODULE : FlexCAN */
\r
1410 /****************************************************************************/
\r
1411 #include "ip_flexcan.h"
\r
1413 /****************************************************************************/
\r
1414 /* MODULE : i2c */
\r
1415 /****************************************************************************/
\r
1423 } IBAD; /* Module Bus Address Register */
\r
1430 } IBFD; /* Module Bus Frequency Register */
\r
1442 vuint8_t IBDOZE:1;
\r
1444 } IBCR; /* Module Bus Control Register */
\r
1458 } IBSR; /* Module Status Register */
\r
1465 } IBDR; /* Module Data Register */
\r
1473 } IBIC; /* Module Interrupt Configuration Register */
\r
1475 }; /* end of I2C_tag */
\r
1476 /****************************************************************************/
\r
1477 /* MODULE : INTC */
\r
1478 /****************************************************************************/
\r
1488 } MCR; /* Module Configuration Register */
\r
1490 int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
\r
1498 } CPR; /* Current Priority Register */
\r
1500 int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
\r
1505 vuint32_t VTBA:21;
\r
1506 vuint32_t INTVEC:9;
\r
1509 } IACKR; /* Interrupt Acknowledge Register */
\r
1511 int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
\r
1518 } EOIR; /* End of Interrupt Register */
\r
1520 int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
\r
1529 } SSCIR[8]; /* Software Set/Clear Interruput Register */
\r
1531 uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */
\r
1539 } PSR[512]; /* Software Set/Clear Interrupt Register */
\r
1541 }; /* end of INTC_tag */
\r
1542 /****************************************************************************/
\r
1543 /* MODULE : LINFLEX */
\r
1544 /****************************************************************************/
\r
1546 struct LINFLEX_tag {
\r
1563 vuint32_t SLEEP:1;
\r
1566 } LINCR1; /* LINFLEX LIN Control Register 1 */
\r
1582 vuint32_t DBFIE:1;
\r
1583 vuint32_t DBEIE:1;
\r
1588 } LINIER; /* LINFLEX LIN Interrupt Enable Register */
\r
1607 } LINSR; /* LINFLEX LIN Status Register */
\r
1619 vuint32_t IDPEF:1;
\r
1625 } LINESR; /* LINFLEX LIN Error Status Register */
\r
1643 } UARTCR; /* LINFLEX UART Mode Control Register */
\r
1662 } UARTSR; /* LINFLEX UART Mode Status Register */
\r
1674 } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */
\r
1683 } LINOCR; /* LINFLEX LIN Output Compare Register */
\r
1694 } LINTOCR; /* LINFLEX LIN Output Compare Register */
\r
1701 vuint32_t DIV_F:4;
\r
1703 } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */
\r
1710 vuint32_t DIV_M:13;
\r
1712 } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */
\r
1721 } LINCFR; /* LINFLEX LIN Checksum Field Register */
\r
1737 } LINCR2; /* LINFLEX LIN Control Register 2 */
\r
1749 } BIDR; /* LINFLEX Buffer Identifier Register */
\r
1754 vuint32_t DATA3:8;
\r
1755 vuint32_t DATA2:8;
\r
1756 vuint32_t DATA1:8;
\r
1757 vuint32_t DATA0:8;
\r
1759 } BDRL; /* LINFLEX Buffer Data Register Least Significant */
\r
1764 vuint32_t DATA7:8;
\r
1765 vuint32_t DATA6:8;
\r
1766 vuint32_t DATA5:8;
\r
1767 vuint32_t DATA4:8;
\r
1769 } BDRM; /* LINFLEX Buffer Data Register Most Significant */
\r
1778 } IFER; /* LINFLEX Identifier Filter Enable Register */
\r
1787 } IFMI; /* LINFLEX Identifier Filter Match Index Register */
\r
1796 } IFMR; /* LINFLEX Identifier Filter Mode Register */
\r
1809 } IFCR[16]; /* LINFLEX Identifier Filter Control Register 0-15 */
\r
1811 }; /* end of LINFLEX_tag */
\r
1812 /****************************************************************************/
\r
1814 /****************************************************************************/
\r
1820 vuint32_t S_CURRENTMODE:4;
\r
1821 vuint32_t S_MTRANS:1;
\r
1824 vuint32_t S_PDO:1;
\r
1826 vuint32_t S_MVR:1;
\r
1827 vuint32_t S_DFLA:2;
\r
1828 vuint32_t S_CFLA:2;
\r
1830 vuint32_t S_FMPLL:1;
\r
1831 vuint32_t S_FXOSC:1;
\r
1832 vuint32_t S_FIRC:1;
\r
1833 vuint32_t S_SYSCLK:4;
\r
1835 } GS; /* Global Status Register */
\r
1840 vuint32_t TARGET_MODE:4;
\r
1844 } MCTL; /* Mode Control Register */
\r
1850 vuint32_t STANDBY0:1;
\r
1852 vuint32_t STOP0:1;
\r
1854 vuint32_t HALT0:1;
\r
1862 vuint32_t RESET:1;
\r
1864 } MER; /* Mode Enable Register */
\r
1870 vuint32_t I_CONF:1;
\r
1871 vuint32_t I_MODE:1;
\r
1872 vuint32_t I_SAFE:1;
\r
1873 vuint32_t I_MTC:1;
\r
1875 } IS; /* Interrupt Status Register */
\r
1881 vuint32_t M_CONF:1;
\r
1882 vuint32_t M_MODE:1;
\r
1883 vuint32_t M_SAFE:1;
\r
1884 vuint32_t M_MTC:1;
\r
1886 } IM; /* Interrupt Mask Register */
\r
1892 vuint32_t S_MTI:1;
\r
1893 vuint32_t S_MRI:1;
\r
1894 vuint32_t S_DMA:1;
\r
1895 vuint32_t S_NMA:1;
\r
1896 vuint32_t S_SEA:1;
\r
1898 } IMTS; /* Invalid Mode Transition Status Register */
\r
1904 vuint32_t MPH_BUSY:1;
\r
1906 vuint32_t PMC_PROG:1;
\r
1907 vuint32_t CORE_DBG:1;
\r
1911 vuint32_t FMPLL_SC:1;
\r
1912 vuint32_t FXOSC_SC:1;
\r
1913 vuint32_t FIRC_SC:1;
\r
1915 vuint32_t SYSCLK_SW:1;
\r
1916 vuint32_t DFLASH_SC:1;
\r
1917 vuint32_t CFLASH_SC:1;
\r
1918 vuint32_t CDP_PRPH_0_143:1;
\r
1920 vuint32_t CDP_PRPH_96_127:1;
\r
1921 vuint32_t CDP_PRPH_64_95:1;
\r
1922 vuint32_t CDP_PRPH_32_63:1;
\r
1923 vuint32_t CDP_PRPH_0_31:1;
\r
1925 } DMTS; /* Invalid Mode Transition Status Register */
\r
1927 int32_t ME_reserved0;
\r
1935 vuint32_t MVRON:1;
\r
1936 vuint32_t DFLAON:2;
\r
1937 vuint32_t CFLAON:2;
\r
1939 vuint32_t FMPLLON:1;
\r
1940 vuint32_t FXOSC0ON:1;
\r
1941 vuint32_t FIRCON:1;
\r
1942 vuint32_t SYSCLK:4;
\r
1944 } RESET; /* Reset Mode Configuration Register */
\r
1952 vuint32_t MVRON:1;
\r
1953 vuint32_t DFLAON:2;
\r
1954 vuint32_t CFLAON:2;
\r
1956 vuint32_t FMPLLON:1;
\r
1957 vuint32_t FXOSC0ON:1;
\r
1958 vuint32_t FIRCON:1;
\r
1959 vuint32_t SYSCLK:4;
\r
1961 } TEST; /* Test Mode Configuration Register */
\r
1969 vuint32_t MVRON:1;
\r
1970 vuint32_t DFLAON:2;
\r
1971 vuint32_t CFLAON:2;
\r
1973 vuint32_t FMPLLON:1;
\r
1974 vuint32_t FXOSC0ON:1;
\r
1975 vuint32_t FIRCON:1;
\r
1976 vuint32_t SYSCLK:4;
\r
1978 } SAFE; /* Safe Mode Configuration Register */
\r
1986 vuint32_t MVRON:1;
\r
1987 vuint32_t DFLAON:2;
\r
1988 vuint32_t CFLAON:2;
\r
1990 vuint32_t FMPLLON:1;
\r
1991 vuint32_t FXOSC0ON:1;
\r
1992 vuint32_t FIRCON:1;
\r
1993 vuint32_t SYSCLK:4;
\r
1995 } DRUN; /* DRUN Mode Configuration Register */
\r
2003 vuint32_t MVRON:1;
\r
2004 vuint32_t DFLAON:2;
\r
2005 vuint32_t CFLAON:2;
\r
2007 vuint32_t FMPLLON:1;
\r
2008 vuint32_t FXOSC0ON:1;
\r
2009 vuint32_t FIRCON:1;
\r
2010 vuint32_t SYSCLK:4;
\r
2012 } RUN[4]; /* RUN 0->4 Mode Configuration Register */
\r
2020 vuint32_t MVRON:1;
\r
2021 vuint32_t DFLAON:2;
\r
2022 vuint32_t CFLAON:2;
\r
2024 vuint32_t FMPLLON:1;
\r
2025 vuint32_t FXOSC0ON:1;
\r
2026 vuint32_t FIRCON:1;
\r
2027 vuint32_t SYSCLK:4;
\r
2029 } HALT0; /* HALT0 Mode Configuration Register */
\r
2031 int32_t ME_reserved1;
\r
2039 vuint32_t MVRON:1;
\r
2040 vuint32_t DFLAON:2;
\r
2041 vuint32_t CFLAON:2;
\r
2043 vuint32_t FMPLLON:1;
\r
2044 vuint32_t FXOSC0ON:1;
\r
2045 vuint32_t FIRCON:1;
\r
2046 vuint32_t SYSCLK:4;
\r
2048 } STOP0; /* STOP0 Mode Configuration Register */
\r
2050 int32_t ME_reserved2[2];
\r
2058 vuint32_t MVRON:1;
\r
2059 vuint32_t DFLAON:2;
\r
2060 vuint32_t CFLAON:2;
\r
2062 vuint32_t FMPLLON:1;
\r
2063 vuint32_t FXOSC0ON:1;
\r
2064 vuint32_t FIRCON:1;
\r
2065 vuint32_t SYSCLK:4;
\r
2067 } STANDBY0; /* STANDBY0 Mode Configuration Register */
\r
2069 int32_t ME_reserved3[2];
\r
2075 vuint32_t S_FLEXCAN5:1;
\r
2076 vuint32_t S_FLEXCAN4:1;
\r
2077 vuint32_t S_FLEXCAN3:1;
\r
2078 vuint32_t S_FLEXCAN2:1;
\r
2079 vuint32_t S_FLEXCAN1:1;
\r
2080 vuint32_t S_FLEXCAN0:1;
\r
2082 vuint32_t S_DSPI2:1;
\r
2083 vuint32_t S_DSPI1:1;
\r
2084 vuint32_t S_DSPI0:1;
\r
2087 } PS0; /* Peripheral Status Register 0 */
\r
2093 vuint32_t S_CANSAMPLER:1;
\r
2095 vuint32_t S_CTU:1;
\r
2097 vuint32_t S_LINFLEX3:1;
\r
2098 vuint32_t S_LINFLEX2:1;
\r
2099 vuint32_t S_LINFLEX1:1;
\r
2100 vuint32_t S_LINFLEX0:1;
\r
2102 vuint32_t S_I2C:1;
\r
2104 vuint32_t S_ADC:1;
\r
2106 } PS1; /* Peripheral Status Register 1 */
\r
2112 vuint32_t S_PIT_RTI:1;
\r
2113 vuint32_t S_RTC_API:1;
\r
2115 vuint32_t S_EMIOS:1;
\r
2117 vuint32_t S_WKUP:1;
\r
2118 vuint32_t S_SIU:1;
\r
2121 } PS2; /* Peripheral Status Register 2 */
\r
2127 vuint32_t S_CMU:1;
\r
2130 } PS3; /* Peripheral Status Register 3 */
\r
2132 int32_t ME_reserved4[4];
\r
2145 vuint32_t RESET:1;
\r
2147 } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */
\r
2153 vuint32_t STANDBY0:1;
\r
2155 vuint32_t STOP0:1;
\r
2157 vuint32_t HALT0:1;
\r
2160 } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */
\r
2167 vuint8_t LP_CFG:3;
\r
2168 vuint8_t RUN_CFG:3;
\r
2170 } PCTL[144]; /* Peripheral Control 0->143 Register */
\r
2172 }; /* end of ME_tag */
\r
2173 /****************************************************************************/
\r
2174 /* MODULE : MPU */
\r
2175 /****************************************************************************/
\r
2180 vuint32_t SPERR:8;
\r
2188 } CESR; /* Module Control/Error Status Register */
\r
2190 uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */
\r
2195 vuint32_t EADDR:32;
\r
2202 vuint32_t EACD:16;
\r
2205 vuint32_t EATTR:3;
\r
2213 vuint32_t EADDR:32;
\r
2220 vuint32_t EACD:16;
\r
2223 vuint32_t EATTR:3;
\r
2231 vuint32_t EADDR:32;
\r
2238 vuint32_t EACD:16;
\r
2241 vuint32_t EATTR:3;
\r
2249 vuint32_t EADDR:32;
\r
2256 vuint32_t EACD:16;
\r
2259 vuint32_t EATTR:3;
\r
2264 uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */
\r
2270 vuint32_t SRTADDR:27;
\r
2273 } WORD0; /* Region Descriptor n Word 0 */
\r
2278 vuint32_t ENDADDR:27;
\r
2281 } WORD1; /* Region Descriptor n Word 1 */
\r
2307 } WORD2; /* Region Descriptor n Word 2 */
\r
2313 vuint32_t PIDMASK:8;
\r
2317 } WORD3; /* Region Descriptor n Word 3 */
\r
2321 uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */
\r
2347 } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
\r
2349 }; /* end of MPU_tag */
\r
2350 /****************************************************************************/
\r
2351 /* MODULE : PCU */
\r
2352 /****************************************************************************/
\r
2359 vuint32_t STBY0:1;
\r
2361 vuint32_t STOP0:1;
\r
2363 vuint32_t HALT0:1;
\r
2373 } PCONF[3]; /* Power domain 0-2 configuration register */
\r
2375 int32_t PCU_reserved0[13]; /* (0x040 - 0x00C)/4 = 0x0D */
\r
2385 } PSTAT; /* Power Domain Status Register */
\r
2387 int32_t PCU_reserved1[15]; /* {0x0080-0x0044}/0x4 = 0xF */
\r
2393 vuint32_t MASK_LVDHV5:1;
\r
2395 } VCTL; /* Voltage Regulator Control Register */
\r
2397 }; /* end of PCU_tag */
\r
2398 /****************************************************************************/
\r
2399 /* MODULE : pit */
\r
2400 /****************************************************************************/
\r
2411 uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */
\r
2446 }; /* end of PIT_tag */
\r
2447 /****************************************************************************/
\r
2448 /* MODULE : RGM */
\r
2449 /****************************************************************************/
\r
2455 vuint16_t F_EXR:1;
\r
2457 vuint16_t F_FLASH:1;
\r
2458 vuint16_t F_LVD45:1;
\r
2459 vuint16_t F_CMU_FHL:1;
\r
2460 vuint16_t F_CMU_OLR:1;
\r
2461 vuint16_t F_FMPLL:1;
\r
2462 vuint16_t F_CHKSTOP:1;
\r
2463 vuint16_t F_SOFT:1;
\r
2464 vuint16_t F_CORE:1;
\r
2465 vuint16_t F_JTAG:1;
\r
2467 } FES; /* Functional Event Status */
\r
2472 vuint16_t F_POR:1;
\r
2474 vuint16_t F_LVD27:1;
\r
2475 vuint16_t F_SWT:1;
\r
2476 vuint16_t F_LVD12_PD1:1;
\r
2477 vuint16_t F_LVD12_PD0:1;
\r
2479 } DES; /* Destructive Event Status */
\r
2484 vuint16_t D_EXR:1;
\r
2486 vuint16_t D_FLASH:1;
\r
2487 vuint16_t D_LVD45:1;
\r
2488 vuint16_t D_CMU_FHL:1;
\r
2489 vuint16_t D_CMU_OLR:1;
\r
2490 vuint16_t D_FMPLL:1;
\r
2491 vuint16_t D_CHKSTOP:1;
\r
2492 vuint16_t D_SOFT:1;
\r
2493 vuint16_t D_CORE:1;
\r
2494 vuint16_t D_JTAG:1;
\r
2496 } FERD; /* Functional Event Reset Disable */
\r
2501 vuint16_t D_POR:1;
\r
2503 vuint16_t D_LVD27:1;
\r
2504 vuint16_t D_SWT:1;
\r
2505 vuint16_t D_LVD12_PD1:1;
\r
2506 vuint16_t D_LVD12_PD0:1;
\r
2508 } DERD; /* Destructive Event Reset Disable */
\r
2510 int16_t RGM_reserved0[4];
\r
2515 vuint16_t AR_EXR:1;
\r
2517 vuint16_t AR_FLASH:1;
\r
2518 vuint16_t AR_LVD45:1;
\r
2519 vuint16_t AR_CMU_FHL:1;
\r
2520 vuint16_t AR_CMU_OLR:1;
\r
2521 vuint16_t AR_FMPLL:1;
\r
2522 vuint16_t AR_CHKSTOP:1;
\r
2523 vuint16_t AR_SOFT:1;
\r
2524 vuint16_t AR_CORE:1;
\r
2525 vuint16_t AR_JTAG:1;
\r
2527 } FEAR; /* Functional Event Alternate Request */
\r
2533 vuint16_t AR_LVD27:1;
\r
2534 vuint16_t AR_SWT:1;
\r
2535 vuint16_t AR_LVD12_PD1:1;
\r
2536 vuint16_t AR_LVD12_PD0:1;
\r
2538 } DEAR; /* Destructive Event Alternate Request */
\r
2540 int16_t RGM_reserved1[2];
\r
2546 vuint16_t SS_LVD45:1;
\r
2547 vuint16_t SS_CMU_FHL:1;
\r
2548 vuint16_t SS_CMU_OLR:1;
\r
2549 vuint16_t SS_PLL:1;
\r
2550 vuint16_t SS_CHKSTOP:1;
\r
2551 vuint16_t SS_SOFT:1;
\r
2552 vuint16_t SS_CORE:1;
\r
2553 vuint16_t SS_JTAG:1;
\r
2555 } FESS; /* Functional Event Short Sequence */
\r
2561 vuint16_t BOOT_FROM_BKP_RAM:1;
\r
2564 } STDBY; /* STANDBY reset sequence */
\r
2569 vuint16_t BE_EXR:1;
\r
2571 vuint16_t BE_FLASH:1;
\r
2572 vuint16_t BE_LVD45:1;
\r
2573 vuint16_t BE_CMU_FHL:1;
\r
2574 vuint16_t BE_CMU_OLR:1;
\r
2575 vuint16_t BE_FMPLL:1;
\r
2576 vuint16_t BE_CHKSTOP:1;
\r
2577 vuint16_t BE_SOFT:1;
\r
2578 vuint16_t BE_CORE:1;
\r
2579 vuint16_t BE_JTAG:1;
\r
2581 } FBRE; /* Functional Bidirectional Reset Enable */
\r
2583 }; /* end of RGM_tag */
\r
2584 /****************************************************************************/
\r
2585 /* MODULE : RTC */
\r
2586 /****************************************************************************/
\r
2594 } RTCSUPV; /* RTC Supervisor Control Register */
\r
2599 vuint32_t CNTEN:1;
\r
2600 vuint32_t RTCIE:1;
\r
2601 vuint32_t FRZEN:1;
\r
2602 vuint32_t ROVREN:1;
\r
2603 vuint32_t RTCVAL:12;
\r
2604 vuint32_t APIEN:1;
\r
2605 vuint32_t APIIE:1;
\r
2606 vuint32_t CLKSEL:2;
\r
2607 vuint32_t DIV512EN:1;
\r
2608 vuint32_t DIV32EN:1;
\r
2609 vuint32_t APIVAL:10;
\r
2611 } RTCC; /* RTC Control Register */
\r
2621 vuint32_t ROVRF:1;
\r
2624 } RTCS; /* RTC Status Register */
\r
2629 vuint32_t RTCCNT:32;
\r
2631 } RTCCNT; /* RTC Counter Register */
\r
2633 }; /* end of RTC_tag */
\r
2634 /****************************************************************************/
\r
2635 /* MODULE : SIU */
\r
2636 /****************************************************************************/
\r
2639 int32_t SIU_reserved0; /* {0x004-0x000}/4 = 0x01 */
\r
2641 union { /* MCU ID Register 1 */
\r
2644 vuint32_t PARTNUM:16;
\r
2648 vuint32_t MAJOR_MASK:4;
\r
2649 vuint32_t MINOR_MASK:4;
\r
2653 union { /* MCU ID Register 2 */
\r
2657 vuint32_t FLASH_SIZE_1:4;
\r
2658 vuint32_t FLASH_SIZE_2:4;
\r
2660 vuint32_t PARTNUM:8;
\r
2667 int32_t SIU_reserved1[2]; /* {0x014-0x00C}/4 = 0x02 */
\r
2669 union { /* Interrupt Status Flag Register */
\r
2673 vuint32_t EIF15:1;
\r
2674 vuint32_t EIF14:1;
\r
2675 vuint32_t EIF13:1;
\r
2676 vuint32_t EIF12:1;
\r
2677 vuint32_t EIF11:1;
\r
2678 vuint32_t EIF10:1;
\r
2692 union { /* Interrupt Request Enable Register */
\r
2696 vuint32_t EIRE15:1;
\r
2697 vuint32_t EIRE14:1;
\r
2698 vuint32_t EIRE13:1;
\r
2699 vuint32_t EIRE12:1;
\r
2700 vuint32_t EIRE11:1;
\r
2701 vuint32_t EIRE10:1;
\r
2702 vuint32_t EIRE9:1;
\r
2703 vuint32_t EIRE8:1;
\r
2704 vuint32_t EIRE7:1;
\r
2705 vuint32_t EIRE6:1;
\r
2706 vuint32_t EIRE5:1;
\r
2707 vuint32_t EIRE4:1;
\r
2708 vuint32_t EIRE3:1;
\r
2709 vuint32_t EIRE2:1;
\r
2710 vuint32_t EIRE1:1;
\r
2711 vuint32_t EIRE0:1;
\r
2715 int32_t SIU_reserved2[3]; /* {0x028-0x01C}/4 = 0x03 */
\r
2717 union { /* Interrupt Rising-Edge Event Enable Register */
\r
2721 vuint32_t IREE15:1;
\r
2722 vuint32_t IREE14:1;
\r
2723 vuint32_t IREE13:1;
\r
2724 vuint32_t IREE12:1;
\r
2725 vuint32_t IREE11:1;
\r
2726 vuint32_t IREE10:1;
\r
2727 vuint32_t IREE9:1;
\r
2728 vuint32_t IREE8:1;
\r
2729 vuint32_t IREE7:1;
\r
2730 vuint32_t IREE6:1;
\r
2731 vuint32_t IREE5:1;
\r
2732 vuint32_t IREE4:1;
\r
2733 vuint32_t IREE3:1;
\r
2734 vuint32_t IREE2:1;
\r
2735 vuint32_t IREE1:1;
\r
2736 vuint32_t IREE0:1;
\r
2740 union { /* Interrupt Falling-Edge Event Enable Register */
\r
2744 vuint32_t IFEE15:1;
\r
2745 vuint32_t IFEE14:1;
\r
2746 vuint32_t IFEE13:1;
\r
2747 vuint32_t IFEE12:1;
\r
2748 vuint32_t IFEE11:1;
\r
2749 vuint32_t IFEE10:1;
\r
2750 vuint32_t IFEE9:1;
\r
2751 vuint32_t IFEE8:1;
\r
2752 vuint32_t IFEE7:1;
\r
2753 vuint32_t IFEE6:1;
\r
2754 vuint32_t IFEE5:1;
\r
2755 vuint32_t IFEE4:1;
\r
2756 vuint32_t IFEE3:1;
\r
2757 vuint32_t IFEE2:1;
\r
2758 vuint32_t IFEE1:1;
\r
2759 vuint32_t IFEE0:1;
\r
2763 union { /* Interrupt Filter Enable Register */
\r
2767 vuint32_t IFE15:1;
\r
2768 vuint32_t IFE14:1;
\r
2769 vuint32_t IFE13:1;
\r
2770 vuint32_t IFE12:1;
\r
2771 vuint32_t IFE11:1;
\r
2772 vuint32_t IFE10:1;
\r
2786 int32_t SIU_reserved3[3]; /* {0x040-0x034}/4 = 0x03 */
\r
2788 union { /* Pad Configuration Registers */
\r
2807 int32_t SIU_reserved4[242]; /* {0x500-0x136}/0xF2 */
\r
2809 union { /* Pad Selection for Multiplexed Input Register */
\r
2813 vuint8_t PADSEL:4;
\r
2817 int32_t SIU_reserved5[56]; /* {0x600-0x520}/4 = 0x38 */
\r
2819 union { /* GPIO Pin Data Output Registers */
\r
2827 int32_t SIU_reserved6[97]; /* {0x800-0x67C}/4 = 0x61 */
\r
2829 union { /* GPIO Pin Data Input Registers */
\r
2837 int32_t SIU_reserved7[225]; /* {0xC00-0x87C}/0x4 = 0xE1 */
\r
2839 union { /* Parallel GPIO Pin Data Output Register */
\r
2842 vuint32_t PPD0:32;
\r
2846 int32_t SIU_reserved8[12]; /* {0xC40-0xC10}/0x4 = 0x0C */
\r
2848 union { /* Parallel GPIO Pin Data Input Register */
\r
2851 vuint32_t PPDI:32;
\r
2855 int32_t SIU_reserved9[12]; /* {0xC80-0xC50}/0x4 = 0x0C */
\r
2857 union { /* Masked Parallel GPIO Pin Data Out Register */
\r
2860 vuint32_t MASK:16;
\r
2861 vuint32_t MPPDO:16;
\r
2865 int32_t SIU_reserved10[216]; /* {0x1000-0x0CA0}/4 = 0xD8 */
\r
2867 union { /* Interrupt Filter Maximum Counter Register */
\r
2871 vuint32_t MAXCNT:4;
\r
2875 int32_t SIU_reserved11[16]; /* {0x1080-0x1040}/4 = 0x10 */
\r
2877 union { /* Interrupt Filter Clock Prescaler Register */
\r
2885 }; /* end of SIU_tag */
\r
2886 /****************************************************************************/
\r
2887 /* MODULE : SSCM */
\r
2888 /****************************************************************************/
\r
2896 vuint16_t BMODE:3;
\r
2901 } STATUS; /* Status Register */
\r
2906 vuint16_t SRAM_SIZE:5;
\r
2912 } MEMCONFIG; /* System Memory Configuration Register */
\r
2914 int16_t SSCM_reserved;
\r
2923 } ERROR; /* Error Configuration Register */
\r
2925 int16_t SSCM_reserved1[2];
\r
2930 vuint32_t PWD_HI:32;
\r
2932 } PWCMPH; /* Password Comparison Register High Word */
\r
2937 vuint32_t PWD_LO:32;
\r
2939 } PWCMPL; /* Password Comparison Register Low Word */
\r
2941 }; /* end of SSCM_tag */
\r
2942 /****************************************************************************/
\r
2943 /* MODULE : STM */
\r
2944 /****************************************************************************/
\r
2945 struct STM_CHANNEL_tag {
\r
2953 } CCR; /* STM Channel Control Register */
\r
2961 } CIR; /* STM Channel Interrupt Register */
\r
2965 } CMP; /* STM Channel Compare Register 0 */
\r
2967 int32_t STM_CHANNEL_reserved;
\r
2969 }; /* end of STM_CHANNEL_tag */
\r
2982 } CR; /* STM Control Register */
\r
2986 } CNT; /* STM Count Register */
\r
2988 int32_t STM_reserved[2];
\r
2990 struct STM_CHANNEL_tag CH[4];
\r
2992 }; /* end of STM_tag */
\r
2993 /****************************************************************************/
\r
2994 /* MODULE : SWT */
\r
2995 /****************************************************************************/
\r
3019 } CR; /* SWT Control Register */
\r
3027 } IR; /* SWT Interrupt Register */
\r
3034 } TO; /* SWT Time-Out Register */
\r
3041 } WN; /* SWT Window Register */
\r
3049 } SR; /* SWT Service Register */
\r
3056 } CO; /* SWT Counter Output Register */
\r
3058 }; /* end of SWT_tag */
\r
3059 /****************************************************************************/
\r
3060 /* MODULE : WKUP */
\r
3061 /****************************************************************************/
\r
3067 vuint32_t NOVF0:1;
\r
3070 } NSR; /* NMI Status Register */
\r
3072 int32_t WKUP_reserved;
\r
3077 vuint32_t NLOCK:1;
\r
3086 } NCR; /* NMI Configuration Register */
\r
3088 int32_t WKUP_reserved1[2];
\r
3096 } WISR; /* Wakeup/Interrupt Status Flag Register */
\r
3102 vuint32_t EIRE:20;
\r
3104 } IRER; /* Interrupt Request Enable Register */
\r
3112 } WRER; /* Wakeup Request Enable Register */
\r
3114 int32_t WKUP_reserved2[2];
\r
3120 vuint32_t IREE:20;
\r
3122 } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */
\r
3128 vuint32_t IFEE:20;
\r
3130 } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */
\r
3138 } WIFER; /* Wakeup/Interrupt Filter Enable Register */
\r
3144 vuint32_t IPUE:20;
\r
3146 } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
\r
3148 }; /* end of WKUP_tag */
\r
3149 /******************************************************************
\r
3150 | defines and macros (scope: module-local)
\r
3151 |-----------------------------------------------------------------*/
\r
3152 /* Define instances of modules */
\r
3153 #define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL)
\r
3154 #define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
\r
3155 #define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
\r
3156 #define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
\r
3157 #define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
\r
3158 #define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
\r
3159 #define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
\r
3160 #define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
\r
3161 #define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
\r
3162 #define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
\r
3163 #define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
\r
3164 #define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
\r
3165 #define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
\r
3166 #define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
\r
3167 #define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
\r
3168 #define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
\r
3169 #define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
\r
3170 #define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
\r
3171 #define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
\r
3172 #define I2C (*(volatile struct I2C_tag *) 0xFFE30000UL)
\r
3173 #define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
\r
3174 #define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL)
\r
3175 #define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL)
\r
3176 #define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
\r
3177 #define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
\r
3178 #define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
\r
3179 #define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
\r
3180 #define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
\r
3181 #define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
\r
3182 #define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
\r
3183 #define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
\r
3184 #define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
\r
3185 #define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
\r
3186 #define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
\r
3187 #define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
\r
3188 #define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
\r
3195 #ifdef __cplusplus
\r
3200 #endif /* ifdef _MPC5604B_H */
\r
3202 /* End of file */
\r
projects / arc.git / blob