drm: xlnx: zynqmp: Disable a plane when the fb format changes
The drm core doesn't explicitly disable a plane when format changes.
So add a check in the plane update functions if the new framebuffer
format has changed, and disable the plane for the format change.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Tested-by: Kuldeep Dave <kuldeepd@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The driver's suspend/resume functions were buggy.
If UART node contains any child node in the DT and
the child is established a communication path with
the parent UART. The relevant /dev/ttyPS* node will
be not available for other operations.
If the driver is trying to do any operations like
suspend/resume without checking the tty->dev status
it leads to the kernel crash/hang.
This patch fix this issue by call the device_may_wake()
with the generic parameter of type struct device.
in the uart suspend and resume paths.
It also fixes a race condition in the uart suspend
path(i.e uart_suspend_port() should be called at the
end of cdns_uart_suspend API this path updates the same)
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Thu, 29 Mar 2018 00:49:19 +0000 (17:49 -0700)]
drm: xlnx: drv: Shutdown the drm device properly
If a drm device is released immediately in shutdown callback by calling
drm_put_device(), it gives a warnning as below because there are some
resources, drm gem objects, that are still used by fbdev emulation and
attached to the drm device.
xilinx: v4l2: dma: Bug fix in single plane support
This patch fixes bugs in single plane handling.
a. Passing v4l2 pixel format to framebuffer driver
b. Making dst_icg is zero, though it does not matter
in case of single plane formats
c. Correcting bytes per line for single plane 10 bit
formats
Derek Kiernan [Fri, 23 Mar 2018 19:43:22 +0000 (19:43 +0000)]
misc: xilinx-sdfec: Setting FEC_CODE change
Setting of the FEC_Code (LDPC/Turbo) is decided at using the device tree
only (at design time only), remove the setting of the value in the function
xsdfec_set_turbo and xsdfec_add_ldpc to function xsdfec_parse_of to ensure
that this is OK.
Signed-off-by: Derek Kiernan <Derek.Kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Fri, 23 Mar 2018 19:43:19 +0000 (19:43 +0000)]
misc: xilinx-sdfec: Memory leak fix
In function xsdfec_add_ldpc and xsdfec_get_ldpc_code_params all failures
after successfully allocating "ldpc/ldpc_params" memory should free the
allocated memory before returning from the function.
Signed-off-by: Derek Kiernan <Derek.Kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Derek Kiernan [Thu, 15 Mar 2018 17:39:17 +0000 (17:39 +0000)]
misc: xilinx-sdfec: Fix open_count decrement when already open
In function xsdfec_dev_open if the atomic_dec_and_test detects that driver
is already opened a increment is required. This ensures the driver
instance can the reopened after it is released by the user.
Signed-off-by: Derek Kiernan <Derek.Kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Set Dual Role Device Mode by default
This patch enables the dwc3 DRD mode by default. Doing so, will
make the same Image to be used for both Host & Device modes
based on the dr_mode dts parameter.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Wed, 21 Mar 2018 17:18:09 +0000 (10:18 -0700)]
drm: xlnx: zynqmp_dp: Use the correct number of lanes
The number of lanes is configurable, thus the dynamically configured
value should be used instead of hard-coded max number of lanes. Use
the number of assigned lanes correctly.
While at it, don't print an error for phy probe deferral.
v4l: xilinx: dma: Return from mplane handling for enum formats
In current driver implemenataion, it is always falling back to
single plane handling after mplane handling. This patch ensures
that mplane handling return gracefully.
Harini Katakam [Thu, 8 Mar 2018 12:50:51 +0000 (18:20 +0530)]
net: macb: Add PM support
This patch
- Adds power management support.
- Updates macb_suspend/resume and runtime_suspend/resume to work in
full power down conditions.
- Adds wake on LAN support using ARP and removes selection of WOL
support via ethtool suing magic packet. This is because ZynqMP PM
support useswake source selection via sys/devices. WOL support is
enabled based on SoC configuration rather than a devicetree property
because this support is specific to IP version and SoC implementation.
- Updates clock init API and fixes clock API header documentation.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Thu, 8 Mar 2018 12:50:50 +0000 (18:20 +0530)]
net: macb: TSU clock and PTP fixes
Enable transmission and reception of PTP unicast packets.
Add tsu_clk and get the rate for the same from clock framework.
Move definition of tsu_rate to be in sync with master.
Add spinlocks in ptp_remove to avoid issues during suspend/resume.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently, we only use the first receive queue and leave the
remaining DMA descriptor pointers pointing at 0.
Disable unused queues by connecting them to a looped descriptor
chain without free slots.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add RX queue pointer to macb queues to make it accessible for the
multiple queues available. Currently the first RX queue is used.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
With this patch the macb driver first tries to find
the mdio node.
If it is available will create the phy/mdio devices for the
phy/mdio nodes available in the mdio.
If the mdio node is not available it will try to probe the phy nodes
available in the mac nodes as the driver does earlier.
Added phy reset functionality using the gpio. This patch assumes that the phy
reset involves an active high/low pulse for certain duration. So, it expects
device tree parameters for reset pulse duration and reset active low or active
high state.
The flags, when requesting gpio for phy reset, should have direction
reflected in bit 0 (as out) and active low/high reflected in bit 1.
Currently these flags are wrong in the driver. Correct this to use
the GPIOF_OUT_INIT_* definitions already available.
Michal Simek [Mon, 12 Mar 2018 15:13:57 +0000 (16:13 +0100)]
Bluetooth: hci_ll: Extend timeout between start and communication
Extend timeout between bt enable and communication with chip.
Flow control is automatic and driver is responding that device is ready
to accept messages but it doesn't need to be truth. Wait more time to
ensure that communication cat start.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This adds an optional nvmem consumer to get a BD address from an external
source. The BD address is then set in the Bluetooth chip after the
firmware has been loaded.
This has been tested working with a TI CC2560A chip (in a LEGO MINDSTORMS
EV3).
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
David Lechner [Fri, 8 Dec 2017 02:22:19 +0000 (20:22 -0600)]
Bluetooth: hci_ll: Add endianness conversion when setting baudrate
This adds an endianness conversion when setting the baudrate using a
vendor-specific command. Otherwise, bad things might happen on a big-
endian system.
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.
In this particular case, notice that I replaced the
"deliberate fall-through..." comment with a "fall through"
comment, which is what GCC is expecting to find.
Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
David Lechner [Tue, 12 Dec 2017 21:59:16 +0000 (15:59 -0600)]
Bluetooth: hci_ll: add support for setting public address
This adds support for setting the public address on Texas Instruments
Bluetooth chips using a vendor-specific command.
This has been tested on a CC2560A chip. The TI wiki also indicates that
this command should work on TI WL17xx/WL18xx Bluetooth chips.
During review, there was some question as to the correctness of the byte
swapping since TI's documentation is not clear on this matter. This can
be tested with the btmgmt utility from bluez. The adapter must be powered
off to change the address. If the baswap() is omitted, address is reversed.
In case there is a issue in the future, here is the output of btmon during
the command `btmgmt public-addr 00:11:22:33:44:55`:
Bluetooth monitor ver 5.43
= Note: Linux version 4.15.0-rc2-08561-gcb132a1-dirty (armv5tejl) 0.707043
= Note: Bluetooth subsystem version 2.22 0.707091
= New Index: 00:17:E7:BD:1C:8E (Primary,UART,hci0) [hci0] 0.707106
@ MGMT Open: btmgmt (privileged) version 1.14 {0x0002} 0.707124
@ MGMT Open: bluetoothd (privileged) version 1.14 {0x0001} 0.707137
@ MGMT Open: btmon (privileged) version 1.14 {0x0003} 0.707540
@ MGMT Command: Set Public Address (0x0039) plen 6 {0x0002} [hci0] 11.167991
Address: 00:11:22:33:44:55 (CIMSYS Inc)
@ MGMT Event: Command Complete (0x0001) plen 7 {0x0002} [hci0] 11.175681
Set Public Address (0x0039) plen 4
Status: Success (0x00)
Missing options: 0x00000000
@ MGMT Event: Index Removed (0x0005) plen 0 {0x0003} [hci0] 11.175757
@ MGMT Event: Index Removed (0x0005) plen 0 {0x0002} [hci0] 11.175757
@ MGMT Event: Index Removed (0x0005) plen 0 {0x0001} [hci0] 11.175757
= Open Index: 00:17:E7:BD:1C:8E [hci0] 11.176807
< HCI Command: Vendor (0x3f|0x0006) plen 6 [hci0] 11.176975
00 11 22 33 44 55 .."3DU
> HCI Event: Command Complete (0x0e) plen 4 [hci0] 11.188260
Vendor (0x3f|0x0006) ncmd 1
Status: Success (0x00)
...
< HCI Command: Read Local Version Info.. (0x04|0x0001) plen 0 [hci0] 11.189859
> HCI Event: Command Complete (0x0e) plen 12 [hci0] 11.190732
Read Local Version Information (0x04|0x0001) ncmd 1
Status: Success (0x00)
HCI version: Bluetooth 2.1 (0x04) - Revision 0 (0x0000)
LMP version: Bluetooth 2.1 (0x04) - Subversion 6431 (0x191f)
Manufacturer: Texas Instruments Inc. (13)
< HCI Command: Read BD ADDR (0x04|0x0009) plen 0 [hci0] 11.191027
> HCI Event: Command Complete (0x0e) plen 10 [hci0] 11.192101
Read BD ADDR (0x04|0x0009) ncmd 1
Status: Success (0x00)
Address: 00:11:22:33:44:55 (CIMSYS Inc)
...
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
David Lechner [Sun, 3 Dec 2017 02:43:55 +0000 (20:43 -0600)]
Bluetooth: serdev: hci_ll: Wait for CTS instead of using msleep
When a TI Bluetooth chip is reset, it takes about 100ms for the RTS line of
the chip to deassert. For my use case with a TI CC2560A chip, this delay
was not long enough and caused the local UART to never transmit at all (TI
AM1808 SoC UART2).
We can wait for the CTS signal using serdev_device_wait_for_cts() instead
of trying to guess using msleep().
Also changed the comment to be more informative while we are touching this
code.
Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
This commit must be reverted, else loading overlays
from the configfs interface will be fails with the
following errors:
OF: changeset: add_property failed @/__symbols__/...
OF: Error applying changeset (-17)
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Thu, 8 Mar 2018 14:15:00 +0000 (06:15 -0800)]
clk: clk-fixed-factor: Use new macro CLK_OF_DECLARE_DRIVER
Fixed factor clock has two initialization at of_clk_init()
time and also during platform driver probe. So declare the
fixed factor clock with CLK_OF_DECLARE_DRIVER instead of
CLK_OF_DECLARE.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kieran Bingham [Wed, 7 Mar 2018 21:13:29 +0000 (13:13 -0800)]
uvcvideo: Prevent new URBs being processed at stream stop
With asynchronous handling of the URBs from the USB Complete handler, we
get a continual stream of packets being received while we are attempting
to shutdown the stream.
Packets that have already been received and processed are on a
work-queue, but during stream shutdown the URBs that those packets
belong to are killed and free'd.
To prevent this race from causing invalid memory accesses, prevent new
URBs from being processed when uvc_stop_streaming() is called by
introducing a new flag "UVC_QUEUE_STOPPING" into the queue, and checking
this when processing the URB to be queued.
With this, we can flush the work queue, and commence a normal pipe
shutdown. Work tasks that are already queued are processed, but the URBs
are prevented from being re-submitted to the USB stack.
Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Fri, 9 Mar 2018 02:40:11 +0000 (18:40 -0800)]
staging: apf: Add synchronization for DMA-BUF add/remove
DMA-BUF attachment in the APF driver lacked appropriate locking
guarantees. This patch adds those protections to allow for
concurrent attach/detach calls.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dmaengine: xilinx: dma: Program hardware supported buffer length
AXI-DMA IP supports configurable (c_sg_length_width) buffer length
register width, hence read buffer length (xlnx,sg-length-width) DT
property and ensure that driver doesn't program buffer length
exceeding the supported limit. For VDMA and CDMA there is no change.
Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Buffer length is an optional DMA node property. DMA driver will
uses this property to ensure that programmed DMA length doesn't
exceed IP supported buffer length(c_sg_length_width).
Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Thu, 8 Mar 2018 06:00:25 +0000 (22:00 -0800)]
dt-bindings: clock: zynqmp: Correct clock names
Some clocks names were intentionally kept incorrect to
match with Linux clock names for backward compatibility.
As now, clock is complete new driver, this is not required
so use proper names for the clocks.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: otg: don't clear event buffers when changing to Host mode from Device mode
Clearing event buffers when changing from Device mode -> Host mode
may require allocating event buffers again during role swap from
Host mode -> Device mode. Changing the event buffers at runtime are
not triggering events in device mode and also the role swap can happen
at any time. So, better not to clear the event buffers during role
swap instead reuse the previously allocated event buffers.
This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In current implementation there is a bug where min_bpl value
is not satisfying dma alignment. This patch will fix the issue
by aligning the value properly.
Jeffrey Mouroux [Wed, 7 Mar 2018 01:49:39 +0000 (17:49 -0800)]
media: v4l2-core: Update V4L2 framework with new fourcc codes
New fourcc codes have been added to support additional video
memory layout supported by Xilinx Video IP. These have been
added to the V4L2 framework with this patch.
Harini Katakam [Mon, 5 Mar 2018 13:54:36 +0000 (19:24 +0530)]
net: xilinx: axiethernet: Add USXGMII support
This patch adds support for USXGMII IP in axiethernet driver.
This IP has a MAC similar to 10G/25G IP and supports USXGMII phy protocol.
USXGMII phy supports speeds from 10Mbps to 10Gbps. Only one phy speed
can be advertised at a time and this choice is obtained from the user
via a devicetree property. This patch was tested at 1G and 2.5G speeds.
Since the MAC functionality is similar to 10G/25G, the same mac type is
used in the config structure. USXGMII IP requires a GT reset and this is
added to axienet_device_reset with a check based on mac type.
projects / zynq / linux.git / log