]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
Documentation: DT: dma: Add axi-dma buffer length property
authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Thu, 8 Mar 2018 09:48:33 +0000 (15:18 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 16 Mar 2018 07:27:53 +0000 (08:27 +0100)
Buffer length is an optional DMA node property. DMA driver will
uses this property to ensure that programmed DMA length doesn't
exceed IP supported buffer length(c_sg_length_width).

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

index addf422a34dbf401cdfcb475c3844bf89e389f36..487b9e14b2003091e7010f6e1a23600f20243e70 100644 (file)
@@ -42,6 +42,9 @@ Optional properties:
        the hardware.
 Optional properties for AXI DMA:
 - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
+- xlnx,sg-length-width: Should be set to the width of buffer length register as
+       configured in hardware. If this property is missing or has invalid width
+       i.e not in range of 8-23, maximum buffer length width 23 bits is used.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
        It takes following values: