Jeffrey Mouroux [Wed, 7 Mar 2018 01:49:39 +0000 (17:49 -0800)]
media: v4l2-core: Update V4L2 framework with new fourcc codes
New fourcc codes have been added to support additional video
memory layout supported by Xilinx Video IP. These have been
added to the V4L2 framework with this patch.
Harini Katakam [Tue, 6 Mar 2018 08:40:44 +0000 (14:10 +0530)]
net: macb: Remove unnecessary DBW read back from NWCFG
The data bus width field is already set based on MAC capability
using macb_dbw function. Remove this unnecessary read back of that
field which might interfere with the correct implementation.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Tue, 6 Mar 2018 08:40:41 +0000 (14:10 +0530)]
net: macb: Add phy suspend and resume
Add phy suspend and resume in macb suspend/resume paths because this
will put the phy in a clean power down state and bring it back up
during resume. Without this, the link will not come back up properly
and communication will be erratic/packets will be lost.
This is generic and is applicable to all PHYs.
Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Harini Katakam [Mon, 5 Mar 2018 13:54:36 +0000 (19:24 +0530)]
net: xilinx: axiethernet: Add USXGMII support
This patch adds support for USXGMII IP in axiethernet driver.
This IP has a MAC similar to 10G/25G IP and supports USXGMII phy protocol.
USXGMII phy supports speeds from 10Mbps to 10Gbps. Only one phy speed
can be advertised at a time and this choice is obtained from the user
via a devicetree property. This patch was tested at 1G and 2.5G speeds.
Since the MAC functionality is similar to 10G/25G, the same mac type is
used in the config structure. USXGMII IP requires a GT reset and this is
added to axienet_device_reset with a check based on mac type.
net: emaclite: Use __func__ instead of hardcoded name
Switch hardcoded function name with a reference to __func__ making
the code more maintainable. Address below checkpatch warning:
WARNING: Prefer using '"%s...", __func__' to using 'xemaclite_mdio_read',
this function's name, in a string
+ "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
WARNING: Prefer using '"%s...", __func__' to using 'xemaclite_mdio_write',
this function's name, in a string
+ "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n"
Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
XHCI controller may not properly send LFPS.U3_EXIT signalling after
resuming from suspend(D3->D0). To avoid this, lets wait for atleast
1ms after updating the PORTSC_30.PLS to enter U0 from U3. This patch
does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
vdmatest: xilinx: Fix VDMA hang reported in certain resolutions
Avoid enabling circular_park mode for S2MM as it might happen that engine
continuously circles through frame buffers w/o being programmed and lead
to an undesired hang. In loopback it is recommended to use same park mode
configuration for both channels.
Saurabh Sengar [Thu, 1 Mar 2018 09:02:02 +0000 (14:32 +0530)]
drm: xlnx: mixer: Adding mixer 3.0 IP support
Adding mixer 3.0 IP support, this adds one extra overlay layer
ie 8th layer.
Also the logo enable bit is moved to 15th from 8, as 8th bit is
now for 8th newly added layer
fpga: zynqmp: sync driver with xilfpga library enhancements
From 4.0 xilfpga library version onwards it's not required
to strip the Headers for Both Secure and Non-Secure
Bitstream Images created by bootgen.The entry point
interface inside the xilfpga library is changed as follows.
u32 XFpga_PL_BitSream_Load (UINTPTR WrAddr,
UINTPTR KeyAddr, u32 flags);
So the user need not to pass the Size and IV info to the FW.
The FW will collect those parameters from the Image Headers.
Old bootgen command:
bootgen -image bistream.bif -arch ZynqMP -process_bitstream bin
(stripping the Headers).
New bootgen command(2018.1 bootgen):
bootgen -image bitstream.bif -arch zynqmp -o Bitstream.bin
(Without stripping the Headers).
These xilfpga changes are included in PMUFW 1.0 which is required for
running the kernel anyway.
Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeffrey Mouroux [Fri, 23 Feb 2018 19:15:11 +0000 (11:15 -0800)]
dma: xilinx: Update Framebuffer Driver with support for new 8-bit/10-bit formats
New DRM and V4L2 fourcc codes have been added to the driver
table. Some of these codes are novel and not yet fully
reviewed nor accepted by the respective communities.
Rohit Athavale [Fri, 23 Feb 2018 19:15:09 +0000 (11:15 -0800)]
v4l: xilinx-vpss-csc: Support for any-to-any color space converison
With this commit the driver supports RGB, YUV 444, YUV 422 and
YUV 420 media bus formats. This commit also updates the VPSS CSC
color controls for any-to-any conversion. VPSS CSC requires
coefficients to be brought into an RGB style of coefficients
before color controls can be applied and thus shadow coefficients
are used to track the color controls.
This commit extracts the color depth information from the
DT and uses it configuring the clip max and contrast. This
commit also allows the user to specify 8-bit or 10-bit color
depth via the DT.
Rohit Athavale [Fri, 23 Feb 2018 19:15:03 +0000 (11:15 -0800)]
v4l: xilinx-demosaic: Remove Output Video format register
Remove the redundant register for output video format as the Video
Sensor Demosaic IP can only support output video with RGB format.
Also some typos in logging messages are fixed in this commit.
Rajan Vaja [Wed, 28 Feb 2018 18:38:01 +0000 (10:38 -0800)]
firmware: zynqmp: Add sysfs to set shutdown scope
The Linux shutdown functionality implemented via PSCI system_off does
not include an option to set a scope, i.e. which parts of the system to
shut down.
This patch creates sysfs that allows to set the shutdown scope for the
next shutdown request. When the next shutdown is performed, the platform
specific portion of PSCI-system_off can use the chosen shutdown scope.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com> Acked-by: Will Wong <willw@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Sat, 24 Feb 2018 14:02:53 +0000 (06:02 -0800)]
clk: zynqmp: Allow zero divisor value
Zero divider is valid and default for some of ZynqMP
clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
for the clock is set.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Acked-by: Jolly Shah <jollys@xilinx.com> Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
v4l: xilinx: dma: Add scaling and padding factor functions
scaling_factor function returns multiplying factor to calculate
bytes per component based on color format.
For eg. scaling factor of YUV420 8 bit format is 1
so multiplying factor is 1 (8/8)
scaling factor of YUV420 10 bit format is 1.25 (10/8)
padding_factor function returns multiplying factor to calculate
actual width of video according to color format.
For eg. padding factor of YUV420 8 bit format: 8 bits per 1 component
no padding bits here, so multiplying factor is 1
padding factor of YUV422 10 bit format: 32 bits per 3 components
each component is 10 bit and the factor is 32/30
Devarsh Thakkar [Tue, 27 Feb 2018 23:34:55 +0000 (15:34 -0800)]
v4l: xilinx: dma: Fix v4l2 enumeration callback for multiplanar
This fixes issues with v4l2 enumeration callback with multiplanar
formats due to which supported multiplanar formats were not getting
enumerated when using VIDEO_ENUM_FMT ioctl.
The intention of existing implementation for multiplanar formats was
to save in array and return the subset of all the v4l2 formats
supported by attached dma device and the supported media bus format
and also cache the supported media bus format so that for future calls
if same media bus format is called then the v4l2 pixel formats can be
directly returned from the entries saved in the array.
This is acheived now with below changes :
a. Use V4L2 subdev helper functions to query supported media bus
format code.
b. Cache the media bus format also for the condition when it is empty
along with whenever new media bus format is detected.
c. Fix NULL pointer deference error by dynamically allocating
memory for poss_v4l2_fmts.
The current v4l driver supports single plane formats. This patch
will add support to handle multi-planar formats. Updated driver
capabilities to multi-planar, where it can handle both single and
multi-planar formats
Jeffrey Mouroux [Tue, 27 Feb 2018 23:34:52 +0000 (15:34 -0800)]
uapi: media: New fourcc codes needed by Xilinx Video IP
The Xilinx Video Framebuffer DMA IP supports video memory formats
that are not represented in the current V4L2 fourcc library. This
patch adds those missing fourcc codes. This includes both new
8-bit and 10-bit pixel formats.
Rohit Athavale [Tue, 27 Feb 2018 23:34:50 +0000 (15:34 -0800)]
media-bus: uapi: Add YCrCb 420 media bus format
This commit adds a YUV 420 media bus format. Currently, one
doesn't exist. VYYUYY8_1X24 does not describe the way the pixels are
sent over the bus, but is an approximation.
Rohit Athavale [Tue, 27 Feb 2018 23:34:49 +0000 (15:34 -0800)]
media: Add new dt-bindings/vf_codes for supported formats
This commit adds new entries to the exisiting vf_codes that are used
to describe the media bus formats in the DT bindings. The newly added
8-bit and 10-bit color depth related formats will need these updates.
Saurabh Sengar [Tue, 27 Feb 2018 06:06:46 +0000 (11:36 +0530)]
drm: xlnx: pl_disp: Adding semi planar support
Adding semi planar color format support in pl_disp for color aware dma.
Framebuffer driver requires chroma buffer address for semi-planar color
format. As we dont have any separate API call in dmaengine for passing
chroma buffer, we calculate the offset from chroma buffer to luma buffer
and pass it in src_icg along with xt. In framebuffer driver chroma buffer
is calculated based on this offset from luma buffer address.
Rajan Vaja [Mon, 26 Feb 2018 10:19:26 +0000 (02:19 -0800)]
clk: zynqmp: Fix reserved parent comparision
When there is any reserved parent in between parents,
firmware sends DUMMY_PARENT(-2). As all other parent
IDs are unsigned, this needs to be type casted to
unsigned before comparison.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This pincontrol binding ("zynqmp-pm") has been replaced
with new binding ("zynqmp-power"). So remove deperecated
binding. Driver would give an error message in case old
binding is used.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This pincontrol binding ("pinctrl-zynqmp") has been
replaced with new binding ("zynqmp-pinctrl"). So remove
deperecated binding. Driver would give an error message
in case old binding is used.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Fri, 23 Feb 2018 13:31:13 +0000 (05:31 -0800)]
drivers: pinctrl: Update ZynqMP pin control driver
Replace existng pin control driver with a new version
of ZyqnMP pin control driver. This driver queries pin
information from firmware and registers pin control
accordingly instead of using hard coded pin info.
New pin control driver creates group name from function name
by adding postfix so some group names are different than existing
group names. Deprecate old pin control driver and its DT bindings
and use new pin control DT binding in device tree.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Fri, 23 Feb 2018 13:31:12 +0000 (05:31 -0800)]
dt-bindings: pinctrl: Add DT binding doc for new pin control driver
Add documentation for the devicetree binding for the new zynqmp
pin controller driver. This driver fetches pin information from
firmware instead of registering hard coded pins. It also calls
firmware APIs to set pin mux and pin configurations.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manu Gautam [Sun, 25 Feb 2018 07:33:22 +0000 (13:03 +0530)]
usb: dwc3: gadget: Fix PCM1 for ISOC EP with ep->mult less than 3
For isochronous endpoints with ep->mult less than 3, PCM1 value of
trb->size in set incorrectly.
For ep->mult = 2, this is set to 0/-1 and for ep->mult = 1, this is
set to -2. This is because the initial mult is set to ep->mult - 1
instead of 2.
Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: gadget: uvc_video: unlock before submitting a request to ep
There could be chances where the usb_ep_queue() could fail and trigger
complete() handler with error status. In this case, if usb_ep_queue()
is called with lock held and the triggered complete() handler is waiting
for the same lock to be cleared could result in a deadlock situation and
could result in system hang. To aviod this scenerio, call usb_ep_queue()
with lock removed. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: Fix the broken suspend/resume functionality in dwc3
Since the GCTL values are lost after suspend, restore the GCTL
prtcap direction values based on the mode of operation. Doing
so, will fix the host/peripheral functionality after resume.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michael Gill [Wed, 21 Feb 2018 02:16:12 +0000 (18:16 -0800)]
staging: apf: Fix performance issues for DMA-BUf on zynq
In an earlier release, DMA-BUF handling in the apf dma drivers
was modified to remove a prior assumption that the scatterlist
structures returned by attaching to a device would not change
during the period of time between attachment and detachment.
Specifically for the UVC camera driver, this was an invalid
assumption. On zu+, these operations are light weight.
On Zynq, they're extremely heavy, which resulted in a performance
hit on Zynq parts that went unnoticed due to video TRD work having
completely shifted to zu+ parts. This patch replicates the
scatterlists passed back by attachment, rather than assuming that
they stay valid, thus removing the performance hit on zynq that
would come about by repeated attach/detach. This patch also
cleans up some inconsistencies between how apf dma drivers treat
DMA-BUF buffers and CMA buffers, resulting in both being handled
more robustly.
Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bhargav Shah [Wed, 21 Feb 2018 22:26:20 +0000 (03:56 +0530)]
dma: xilinx: Removed unsupported DMA_SG capablity
Commit c678fa66341c on master-next-test is breaking
compilation due to DMA_SG support removal.
This patch removes support for DMA_SG and adds support
for DMA_MEMCPY.
Signed-off-by: Venkata Ravi Shankar <vjonnal@xilinx.com> Signed-off-by: Bhargav Shah <bhargavs@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Bhargav Shah [Wed, 21 Feb 2018 22:26:21 +0000 (03:56 +0530)]
dma: xilinx: Removed unsupported DMA_SG capablity from client driver
DMA_SG is depricated and DMA_MEMCPY is added in platform driver.
Hence, removing support for DMA_SG and adding DMA_MEMCPY support in
client driver.
Signed-off-by: Bhargav Shah <bhargavs@xilinx.com> Signed-off-by: Venkata Ravi Shanker <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Wed, 21 Feb 2018 18:21:27 +0000 (10:21 -0800)]
drm: xlnx: drv: Allow multiple masters on a drm device
This may not be the ideal solution, but is to allow multiple
masters running on a single drm device, when the application
has the admin priviliege. This enables access to master
only resources such as setting drm planes and etc.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saurabh Sengar [Mon, 19 Feb 2018 05:30:26 +0000 (11:00 +0530)]
drm: xlnx: mixer: logo layer fix
This patch fixes the occasional kernel oops when programing logo layer.
Issue was because of accessing/programing wrong memory.
Following fixes corrected this calculation :
- using the currect buffer b_buf instead of r_buf
- correcting the register address calculation by one offset
- corrected pixel_alpha selection based on color format logic
Rohit Athavale [Tue, 20 Feb 2018 18:14:08 +0000 (10:14 -0800)]
media: xilinx-vpss-scaler: Zero out H-phase array before changing resolution
When changing resolutions, the H-phases need to be re-calculated. This
commit zeroes out the H-phase array. This fixes the stretching
(pixel repeat) seen when upscaling video.
Saurabh Sengar [Thu, 15 Feb 2018 19:29:25 +0000 (00:59 +0530)]
drm: xlnx: pl_disp: Adding multiple color format in single plane
Adding multiple color formats in single plane.
In case of framebuffer, color format will be queried from framebuffer
driver and in case of vdma, device tree color format will be the only
color format supported.
Add the PS-PL reset support.There are 4 gpios in bank 5 that
are used as ps to PL reset.
This will be used by the fpga manager to reset after loading the
bit stream.
eg: The design uses 2 resets, then 2 resets will be used by the
fpga manager. The other 2 will be available as GPIOs.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This binding was replaced by new one and it shouldn't be used anywhere.
Clock driver is checking this compatible string but it should be removed
in one or two releases.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Tue, 20 Feb 2018 12:28:37 +0000 (04:28 -0800)]
clk: zynqmp: Use firmware APIs in clock driver
In existing driver, clocks are registered statically.
Instead of using static clocks, get clock information
from firmware and register clocks accordinglly.
Firmware maintains database of all clocks avaiable for the
variant. So if there is any new clocks are avaiable for
specific variant or some clocks are not present in
variant, Linux driver would not need any change.
To contorl the clocks, use firmware APIs instead of
register read/write. This prevents direct clock control
from any single master(processor) shared between multiple
masters. Firmware can implement this APIs to manage
shared clocks.
Change clock IDs in dts based on new firmware IDs.
Signed-off-by: Tejas Patel <tejasp@xilinx.com> Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rajan Vaja [Tue, 20 Feb 2018 12:28:36 +0000 (04:28 -0800)]
dt-bindings: clock: Add bindings for ZynqMP clock driver
Add documentation to describe Xilinx ZynqMP clock driver
bindings.
Signed-off-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>