]> rtime.felk.cvut.cz Git - zynq/linux.git/commitdiff
vdmatest: xilinx: Add hsize and vsize module parameter
authorRadhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Thu, 1 Mar 2018 11:26:01 +0000 (16:56 +0530)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 2 Mar 2018 07:38:39 +0000 (08:38 +0100)
Make the horizontal and vertical length configurable. This allows
VDMA IP to be validated for all supported resolution.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/dma/xilinx/vdmatest.c

index 8d5e8c0ab2009369a6b6c47b489e76cb3c9b0c0e..835b878b0738aa7c12d704e0e3d8bfe081df2b76 100644 (file)
@@ -38,6 +38,14 @@ module_param(iterations, uint, S_IRUGO);
 MODULE_PARM_DESC(iterations,
                "Iterations before stopping test (default: infinite)");
 
+static unsigned int hsize = 64;
+module_param(hsize, uint, 0444);
+MODULE_PARM_DESC(hsize, "Horizontal size in bytes");
+
+static unsigned int vsize = 32;
+module_param(vsize, uint, 0444);
+MODULE_PARM_DESC(vsize, "Vertical size in bytes");
+
 /*
  * Initialization patterns. All bytes in the source buffer has bit 7
  * set, all bytes in the destination buffer has bit 7 cleared.
@@ -237,7 +245,6 @@ static int xilinx_vdmatest_slave_func(void *data)
        enum dma_status status;
        enum dma_ctrl_flags flags;
        int ret = -ENOMEM, i;
-       int hsize = 64, vsize = 32;
        struct xilinx_vdma_config config;
 
        thread_name = current->comm;