drvdata->base_addr + XEL_TSR_OFFSET);
/* Enable the Rx interrupts for the first buffer */
- xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
+ xemaclite_writel(XEL_RSR_RECV_IE_MASK,
+ drvdata->base_addr + XEL_RSR_OFFSET);
/* Enable the Global Interrupt Enable */
- xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
+ xemaclite_writel(XEL_GIER_GIE_MASK,
+ drvdata->base_addr + XEL_GIER_OFFSET);
}
/**
u32 reg_data;
/* Disable the Global Interrupt Enable */
- xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
+ xemaclite_writel(XEL_GIER_GIE_MASK,
+ drvdata->base_addr + XEL_GIER_OFFSET);
/* Disable the Tx interrupts for the first buffer */
reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
/* Update the MAC address in the EmacLite */
reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
- xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
+ xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR,
+ addr + XEL_TSR_OFFSET);
/* Wait for EmacLite to finish with the MAC address update */
while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &
}
/* Check if the Transmission for the second buffer is completed */
- tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
+ tx_status = xemaclite_readl(base_addr +
+ XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
(tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;