v4l: xilinx: scd: Cleanup the DMA engine at remove() time
The resources allocated by the xscd_dma_init() function are never
released. Add a new xscd_dma_cleanup() function to handle the cleanup
and call it at driver remove() time.
v4l: xilinx: scd: Merge the DMA support in the main SCD driver
There's no need to create a separate platform_driver and platform_device
for the DMA support. Merge the xscd_dma_device structure into the
xscd_device. This allows removing duplicating fields, as well as
unneeded code.
v4l: xilinx: scd: Merge the main and V4L2 IRQ handlers
Both the main SCD driver and the V4L2 support code register an IRQ
handler, for the same IRQ. This is unnecessary, we can just call the
V4L2 IRQ handling function from the main IRQ handler.
v4l: xilinx: scd: Merge the V4L2 support in the main SCD driver
There's no need to create a separate platform_driver and platform_device
for the V4L2 support. Call the xilinx-scenechange-channel initialization
function directly from the main driver. This allows removing duplicating
fields, as well as unneeded code.
Move all driver data structures to the xilinx-scenechange.h header. Turn
the cast macros into static inline function and rename them all to
to_<struct name> for consistency.
v4l: xilinx: vipp: Support entity matching on DT subnodes
When the video IP pipeline is parsed in DT, the composite device stores
all entities found in the graph, along with their corresponding DT node.
Later on the DT nodes pointers are used to locate the corresponding V4L2
subdevs by matching them against subdev->dev->of_node.
This mechanism works fine for devices that register a single subdev. For
devices that register multiple subdevs, subdev->dev->of_node points to
the DT node of the device, while the entities parsed from the pipeline
point to child nodes of the device DT node.
The v4l2_subdev structure has a fwnode field that is set to point to the
fwnode corresponding to the device DT node. Drivers that register
multiple subdevs must set the fwnode field manually to the associated
child node of the device DT node. We can thus fix this issue by locating
V4L2 subdevs for an entity based on the subdev fwnode instead of the
dev->of_node.
v4l: xilinx: sdirxss: Fix the media bus formats to 10bpc type
With commit id 563e888fca45a978e4c29b2f5ec5a8a95af60e68, xyavta now
fails to start stream as the media bus format requested is
MEDIA_BUS_FMT_UYVY10_1x20 but the SDI Rx subdev returned media bus
format is MEDIA_BUS_FMT_UYVY8_1x16.
Fix this by updating the driver for correct media bus formats for YUV
422 and 420 10bpc i.e. MEDIA_BUS_FMT_UYVY10_1X20 and
MEDIA_BUS_FMT_VYYUYY10_4X20.
Vishal Sagar [Fri, 29 Mar 2019 06:23:20 +0000 (23:23 -0700)]
v4l: xilinx: tpg: Dynamically modify TPG output format
The TPG output format was fixed based on the device tree. This patch now
allows the TPG output format to be configured at runtime. This is valid
only for the HLS version of TPG.
usb: host: xhci: Add xhci_hcd to xhci_ring for use in stream_timeout_function
This patch modifies the code to pass xhci_hcd in xhci_ring
which would be used by stream_timeout_function() to send
stop command on the stream ring after stream timer gets
timedout.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: otg: Add dependencies required by otg.c and drd.c files
drd.c file supports the simple OTG role swap feature based on the
ULPI pin status and otg.c file supports the TRUE OTG features like
HNP, SRP and also Role swap based on ULPI ID pin.
This patch adds the dependencies required by drd.c and otg.c files.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: otg: Pass dummy address instead of value
dwc3_otg_set_host() stops peripheral mode once the
host initialization is done. The present code logic
detects the host init done based on the value sent
in place of struct usb_bus * ptr. The pointer
value is checked with 0x1 to know whether host is
initialized or not. This patch changes the code
to check against the dummy address value "0xdeadbeef"
instead of value "0x1"
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: otg: Add support for ending HNP session
As a part of sucessful HNP session both A-Device and
B-Device swaps their roles from A-Device: Host->Peripheral
and B-Device: Peripheral->Host. Once the B-Device is done
as Host, the HNP session should be ended to restore to their
previous roles i.e, A-Device: Peripheral->Host and B-Device:
Host->Peripheral. This patch adds a sysfs entry which will
end the HNP session and restore to their original roles.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: route lpd usb traffic through CCI path for making SMMU work
usb dma traffic by default takes the direct DDR path from LPD switch.
Since SMMU is present before CCI, the usb dma traffic needs to be
routed to take the CCI path for making SMMU work. This can be done
by enabling "coherency" in usb.
This patch modifies the code to enable coherency in usb for below
mentioned cases
1. To route usb dma transactions through CCI path for coherency. This is
done when "dma-coherent" property is added into dwc3 dts node.
2. To route usb dma transactions through CCI path to make SMMU work with
usb dma. This is done when "dwc->dev->iommu_group" is populated
(iommu_group is only populated when sucessfull smmu comtext for usb is
created).
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
USB: gadget: f_hid: fix deadlock in f_hidg_write()
In f_hidg_write() the write_spinlock is acquired before calling
usb_ep_queue() which causes a deadlock when dummy_hcd is being used.
This is because dummy_queue() callbacks into f_hidg_req_complete() which
tries to acquire the same spinlock. This is (part of) the backtrace when
the deadlock occurs:
0xffffffffc06b1410 in f_hidg_req_complete
0xffffffffc06a590a in usb_gadget_giveback_request
0xffffffffc06cfff2 in dummy_queue
0xffffffffc06a4b96 in usb_ep_queue
0xffffffffc06b1eb6 in f_hidg_write
0xffffffff8127730b in __vfs_write
0xffffffff812774d1 in vfs_write
0xffffffff81277725 in SYSC_write
Fix this by releasing the write_spinlock before calling usb_ep_queue()
usb: dwc3: otg: mask host/device soft reset from affecting the phy
Setting OCFG.OTGSFTRSTMASK bit masks reset signal issued
either from host or device soft reset from affecting the
reset signal outputs sent to the phy. This patch sets
programs this bit when starting host or peripheral mode
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: otg: make otg driver work along with drd driver
There are 2 drivers which can be used for dwc3 otg feature, they are
discussed below
1. drd.c -> This driver supports the basic Host <-> Peripheral role
swap based on ID PIN sensing. If ID PIN is low the Host
role is switched. When ID PIN is high Peripheral role is
switched
2. otg.c -> This driver is internal driver which supports the TRUE OTG
functionality. Unlike drd.c , this driver supports the OTG
features like HNP (Host Negotiation Protocol) , SRP (Session
Request Protocol) and Host <-> Peripheral swapping (same as
drd.c)
This patch makes the necessary code changes for enabling
otg.c when "CONFIG_USB_DWC3_OTG" is enabled and drd.c when
the "CONFIG_USB_DWC3_DUAL_ROLE" is enabled
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: gadget: Don't kick transfer if LST or SHORT bits are set
When LST bit is set in event->status, indicates that the
transfer is completed and when SHORT bit is set in
event->status, indicates that the transfer completed with
short transfer.
In dwc3_gadget_ep_cleanup_completed_request(), the transfer
should not be started again if any of LST or SHORT bits are
set in the event.This patch modifies the code to check for
LST & SHORT bits before kick starting the transfer
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: Check MISSED ISOC bit only for ISOC endpoints
When streaming is enabled on BULK endpoints and LST bit is set
observed MISSED ISOC bit set in event->status for BULK ep. Since
this bit is only valid for isocronous endpoints, changed the code
to check for isocrnous endpoints when MISSED ISOC bit is set.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields
The present code in dwc3_gadget_ep_reclaim_completed_trb() will check
for IOC/LST bit in the event->status and returns if IOC/LST bit is
set. This logic doesn't work if multiple TRBs are queued per
request and the IOC/LST bit is set on the last TRB of that request.
Consider an example where a queued request has multiple queued TRBs
and IOC/LST bit is set only for the last TRB. In this case, the Core
generates XferComplete/XferInProgress events only for the last TRB
(since IOC/LST are set only for the last TRB). As per the logic in
dwc3_gadget_ep_reclaim_completed_trb() event->status is checked for
IOC/LST bit and returns on the first TRB. This makes the remaining
TRBs left unhandled.
To aviod this, changed the code to check for IOC/LST bits in both
event->status & TRB->ctrl. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: Correct the logic for checking TRB full in __dwc3_prepare_one_trb()
vailability of TRB's is calculated using dwc3_calc_trbs_left(), which
determines total available TRB's based on the HWO bit set in a TRB.
In the present code, __dwc3_prepare_one_trb() is called with a TRB which
needs to be prepared for transfer. This __dwc3_prepare_one_trb() calls
dwc3_calc_trbs_left() to determine total available TRBs and set IOC bit
if the total available TRBs are zero. Since the present working TRB (which
is passed as an argument to __dwc3_prepare_one_trb() ) doesn't yet have
the HWO bit set before calling dwc3_calc_trbs_left(), there are chances
that dwc3_calc_trbs_left() wrongly calculates this present working TRB
as free(since the HWO bit is not yet set) and returns the total available
TRBs as greater than zero (including the present working TRB). This could
be a problem.
This patch corrects the above mentioned problem in __dwc3_prepare_one_trb()
by increementing the dep->trb_enqueue at the last (after preparing the TRB)
instead of increementing at the start and setting the IOC bit only if the
total available TRBs returned by dwc3_calc_trbs_left() is 1 . Since we are
increementing the dep->trb_enqueue at the last, the present working TRB is
also considered as available by dwc3_calc_trbs_left() and non zero value is
returned . So, according to the modified logic, when the total available
TRBs is equal to 1 that means the total available TRBs in the pool are 0.
HNP(Host Negotiation Protocol) is an USB OTG 2.0 feature where the
HOST & DEVICE can swap their roles. Using HNP feature A-device acting
in HOST mode can be role swapped to DEVICE mode and B-device acting in
DEVICE mode can be role swapped to HOST mode.
This feature was broken in earlier releases, so this patch fixes the same
by enabling HNP support before entering into device mode and also avoids
ADevBHostEndEvent getting triggered by waiting for extra time before
enabling events in A-peripheral state, thus giving enough time for HOST
stack on B-device to be loaded.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: gadget: ISOC transfers should be stopped before starting a transfer
For ISOC transfers the requests are not queued until the HOST requests
for data and XferNotReady event is generated .But XferNotReady event
is not getting generated for ISOC transfers for the second time after
Endpoint configuration. Since ISOC packets depend on the XferNotReady
events, they will not be queued to controller. Because of this issue
timeout happens on the application layer.
This patch fixes this issue by issuing END TRANSFER command before
starting any ISOC transfers. Doing so will make the controller clear
the previous allocated endpoint resources and reallocate resources
when the transfer is requested. Because of this change XferNotReady
events will be generated when host requests for the ISOC transfer.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
XHCI controller may not properly send LFPS.U3_EXIT signalling after
resuming from suspend(D3->D0). To avoid this, lets wait for atleast
1ms after updating the PORTSC_30.PLS to enter U0 from U3. This patch
does the same.
usb: dwc3: Correct usb dma mask for making SMMU work in device mode
By default dma_coherent_mask is set to 32 bits, because of this the
virtual address generated by the SMMU is masked to 32 bit width.
Due to this reason, the events generated by the USB DMA are not being
updated to the correct physical address and undefined behaviour is
generated.
This patch corrects the above said problem by reading and setting
the DMA coherent mask based on the GHWPARAMS0.MDWIDTH value.
usb: gadget: uvc_video: unlock before submitting a request to ep
There could be chances where the usb_ep_queue() could fail and trigger
complete() handler with error status. In this case, if usb_ep_queue()
is called with lock held and the triggered complete() handler is waiting
for the same lock to be cleared could result in a deadlock situation and
could result in system hang. To aviod this scenerio, call usb_ep_queue()
with lock removed. This patch does the same.
usb: dwc3: Fix the broken suspend/resume functionality in dwc3
Since the GCTL values are lost after suspend, restore the GCTL
prtcap direction values based on the mode of operation. Doing
so, will fix the host/peripheral functionality after resume.
Due to incorrect programming sequence the "missing peripheral IRQ"
error message gets showed even after finding the correct IRQ.
This patch fixes the code logic for removing this error message
usb: gadget: configfs: Add support for setting maximum supported speed
Since configfs driver determines the current opertaing speed of the
configured usb gadget, add support for setting the maximum_speed
from the configfs directory. This patch does the same.
usb: xhci: don't clean shared_hcd when otg is enabled
Since xhci->shared_hcd contains all the required information
that is needed by otg driver, don't clear the xhci->shared_hcd
during xhci_stop() when otg is enabled
usb: dwc3: don't wait for end transfer to finish for isoc endpoints
Issuing End Transfer command for isocronous endpoints is not
triggering command complete interrupt, so waiting for this
command complete interrupt could endup hanging the system. This
patch modifies the code to not wait for command complete interrupt
after issuing End Transfer command for isoc endpoints.
usb: dwc3: fix the logic for setting GBLHIBERNATIONEN in GCTL
The U3PMU/U2PMU will not save or restore any core state until
GBLHIBERNATIONEN is enabled. This patch fix the code for enabling
GBLHIBERNATIONEN for both host and device mode.
dt-bindings: usb: dwc3: Add flag for supporting hibernation
This patch documents the snps,enable-hibernation devicetree
property , which enables the hibernation support for dwc3
driveer when operating in peripheral mode
usb: dwc3: don't setup event buffers when operating in device mode
This patch skips the initialization of event buffers (which are required
only when USB controller is operation in device or otg mode) when
operating in host only mode.
usb: dwc3: Put usb core in reset after entering D3 state
After entering into D3 mode,the major part of the usb controller except
U3PMU/U2PMU power will be removed.So, it is recommented to put the usb
core in reset after entering D3 mode otherwise undefined behaviour may
occur. This patch does the same.
usb: function: f_tcm: Add support for getting alt interface number
This patch adds support for reading alt interface number using
get_alt() function. This returns '1' if currently UASP interface is
selected by host or '0' if BOT is selected.
snps,refclk_fladj property needs to be added to devicetree node
when frame legth adjustment for SOF/ITP counter needs to be done.
This patch documents the same.
The present logic doesn't fetch the correct parent node when two usb nodes
are enabled. It searches all nodes and doesn't fetch the first node with
matching compatible string when two usb nodes are enabled.
This patch fixes the logic by searching "xlnx,zynqmp-dwc3" compatible
string only in the parent nodes instead of the searching all nodes.
if queue is full we are depending on HWO bit to see if queue is
full or empty. after advancing trb_enqueue last trb will be the
trb we are working right now. so need to check after HWO bit is
set
according to databook it may be possible host and device become
out of sync where device wait for host to issue prime transcation
and host waits for device to issue erdy to avoid such deadlock
timeout need to be implement. after timeout device will first
stop transfer and again restart the transfer
usb: dwc3: enable transfer complete event for stream endpoint
start transfer for new stream id need to free previously held
transfer resources. transfer complete event will automatically
free up the resource once transfer associated with stream
completes
dwc3: Fix the logic used to get data from parent node
At present when two usb nodes are enabled, incorrect simple data is
getting fetched from parent node. Because of this kernel panic was
getting triggered when more than one usb nodes are enabled.
This patch fixes the logic used to get simple data from parent node.
dwc3: Add support for removing vbus when suspended
During suspend, dwc3 host puts the device into U3 state and disables the
clocks. During resume, dwc3 host drives LFPS.polling to detect the
connected usb device and most of the usb devices detect LFPS.polling signal
and drives LFPS.U3 exit signal and gets detected by the dwc3 host. But very
few usb devices during resume doesn't drive u3 exit signalling even after
seeing LFPS.polling signal on the link and wait for the host to initiate an
u3 exit(Currently the USB stack doesn't drive U3 exit during resume from
suspened). These kind of devices doesn't even respond to warm reset
signalling sent by the host. Since these usb devices doesn't respond to
polling or warm reset, host controller doesn't generate USB detect event
after resume from suspend until manual disconnect.
To aviod the above said issue, during suspend we need to ask ULPI phy to
stop driving of VBUS and restore VBUS during resume. Doing so, will make
usb device to enter into RX Detect state and start LFPS.polling after
restoring LFPS.polling signal and thus generating detect event on the host
side.
This patch does the above said with a check to ensure that VBUS is not
disabled for the usb devices that are remote wakeup capable.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dwc3: Add support for clock disabling during suspend
In dwc3 usb controller, when remote wakeup feature is enabled and
the controller is in U3 state (suspended), it requires suspend_clk
to be active to detect wakeup signalling driven on the link.
For all other cases usb clocks can be disabled once the controller
enters U3 state.
This patch adds the logic for disabling usb clocks when remote
wakeup feature is not enabled.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: Add quirk for enabling workaround for BULK IN streams
This patch adds support for enabling workaround for BULK IN stream
rings by adding "xhci-stream-quirk" flag to dts node. Enabling this
flag activates the timer for every BULK IN stream ring at the time
of queuing TRB's into BULK IN stream ring.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: Correct dwc3 host init code for making SMMU work in HOST Mode
DWC3 driver initializes the xhci host platform device structure.
As a part of initialization it configures xhci dev DMA attributes,
but fails to set correct smmu dma ops (if iommus node is added in
dts file). But SMMU driver intializes correct context block based
on the SMMU Stream ID given by USB dts node. Due to the improper
initalization of dma ops(SWIO instead of SMMU) no proper page table
entries are updated in SMMU Contect Block, thus generating an abort
when USB DMA tries to write an event in the event ring.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dwc3: core: Enable GUCTL1 chicken bit 9 for correcting Inter Packet Delay(IPD)
SNPS controller when configureed in HOST mode maintains Inter Packet
Delay (IPD) of ~380ns which works with most of super-speed hubs except
VIA-LAB hubs. When IPD is ~380ns HOST controller fails to enumerate FS/LS
devices when connected behind VIA-LAB hubs.
Enabling bit 9 of GUCTL1 enables the workaround in HW to reduce the ULPI
clock latency by 1 cycle, thus reducing the IPD (~360ns) and making
controller enumerate FS/LS devices connected behind VIA-LAB.
This patch fixes the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dwc3: core: Enable GUCTL1 chicken bit 10 for fixing crc error after resume bug
When configured in HOST mode, after issuing U3/L2 exit controller fails to
send proper CRC checksum in CRC5 feild. Because of this behaviour
Transaction Error is generated, resulting in reset and re-enumeration of
usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this
problem. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dwc3: Add support for setting USB control registers as phy platform data
This patch adds support for setting USB vendor specific control registers
as phy platform data. These registers are used by the phy to configure USB
PIPE signals.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dwc3: dwc3-of-simple: Move ioremap calls into probe
Currently ioremap_resource & ioremap_release of USB vendor specific
control regions are being done in dwc3_enable_hw_coherency() when
CCI is enabled. These USB vendor specific regions has the PIPE3
control registers, which needs to be configured everytime to get
proper connect/disconnect events. Because of this reason moving the
ioremap_resource into probe.
Note:
This patch is a temporary workaround which is done to set pipe signals
without effecting usb cci and this will be redesigned. this change will
get it into v2017.1 and expected to change once the proper solution is
available.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Tue, 28 Mar 2017 10:31:52 +0000 (16:01 +0530)]
usb: dwc3: core: Enable CCI support in dwc3 core driver
This patch adds CCI support in DWC3 driver when CCI is enabled in the
design. There are couple of registers which need to be modified for
making CCI enabled transfers in USB. This patch add the support for
the same.
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Tue, 28 Mar 2017 10:31:51 +0000 (16:01 +0530)]
usb: dwc3: of-simple: Enable CCI support in dwc3 driver
This patch adds CCI support in DWC3 driver when CCI is enabled in the
design. There are couple of registers which need to be modified for
making CCI enabled transfers in USB. This patch add the support for the
same.
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We would know how many scratch buffers to allocate in core_init. So,
move scratch buffer allocation in core_init. Keep a check to avoid
re-allocation when core_init is called after probe.
Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers: dwc3: Fix cleaning of soc_rev for failure conditions
In the current code, we are cleaning soc_rev value even if it
has junk value which occurs because of failure to read SoC revision.
Doing so will trigger in kernel panic. This patch fixes the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers: dwc3: Add U3 suspend disable quirk for silicon versions less than v4
The logic for updating dwc->revision flag got corrected in 4.9 kernel,
which sets USB3PIPECTL.SUSPENDENABLE bit for dwc3 core versions >= 2.90A.
Because of this bit being set we are seeing failure while configuring
endpoints and below error is seen
"Failure to configure ep0out"
When this bit is set the control enables autosuspended of phy. As a part
of this feature controller automatically disables the phy clocking when
it is idle. This issue is observed with silicon revisions < 4.0.
This patch adds "snps,dis_u3_susphy_quirk" into platform node if silicon
revision is found to be less than 4.0
projects / zynq / linux.git / log