v4l: xilinx: scd: Consolidate register definitions

Move all macros defining register offsets and bits to the
xilinx-scenechange.h header, shared between the three source files that
deal with the SCD.

Rename the XSCD_COLOR_FMT_* macros to XSCD_VID_FMT_*, in order to match
the correspongin register name.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>

diff --git a/drivers/media/platform/xilinx/xilinx-scenechange-channel.c b/drivers/media/platform/xilinx/xilinx-scenechange-channel.c
index 6d95e870214b0201a2c1e64888bca4a836cfe7fd..7b54cdbbd9e755d723bc474732cc18f9d5f71f8a 100644 (file)
--- a/drivers/media/platform/xilinx/xilinx-scenechange-channel.c
+++ b/drivers/media/platform/xilinx/xilinx-scenechange-channel.c
@@ -36,23 +36,6 @@
 #define XSCD_MIN_WIDTH         640
 #define XSCD_MIN_HEIGHT                480
 
-#define XSCD_WIDTH_OFFSET              0x10
-#define XSCD_HEIGHT_OFFSET             0x18
-#define XSCD_STRIDE_OFFSET             0x20
-#define XSCD_VID_FMT_OFFSET            0x28
-#define XSCD_SUBSAMPLE_OFFSET          0x30
-#define XSCD_SAD_OFFSET                        0x38
-
-/* Hardware video formats for memory based IP */
-#define XSCD_COLOR_FMT_Y8              24
-#define XSCD_COLOR_FMT_Y10             25
-
-/* Hardware video formats for streaming based IP */
-#define XSCD_COLOR_FMT_RGB             0
-#define XSCD_COLOR_FMT_YUV_444         1
-#define XSCD_COLOR_FMT_YUV_422         2
-#define XSCD_COLOR_FMT_YUV_420         3
-
 #define XSCD_V_SUBSAMPLING             16
 #define XSCD_BYTE_ALIGN                        16
 #define MULTIPLICATION_FACTOR          100
@@ -132,15 +115,15 @@ static int xscd_chan_get_vid_fmt(u32 media_bus_fmt, bool memory_based)
                case MEDIA_BUS_FMT_VYYUYY8_1X24:
                case MEDIA_BUS_FMT_UYVY8_1X16:
                case MEDIA_BUS_FMT_VUY8_1X24:
-                       vid_fmt = XSCD_COLOR_FMT_Y8;
+                       vid_fmt = XSCD_VID_FMT_Y8;
                        break;
                case MEDIA_BUS_FMT_VYYUYY10_4X20:
                case MEDIA_BUS_FMT_UYVY10_1X20:
                case MEDIA_BUS_FMT_VUY10_1X30:
-                       vid_fmt = XSCD_COLOR_FMT_Y10;
+                       vid_fmt = XSCD_VID_FMT_Y10;
                        break;
                default:
-                       vid_fmt = XSCD_COLOR_FMT_Y8;
+                       vid_fmt = XSCD_VID_FMT_Y8;
                }
 
                return vid_fmt;
@@ -150,22 +133,22 @@ static int xscd_chan_get_vid_fmt(u32 media_bus_fmt, bool memory_based)
        switch (media_bus_fmt) {
        case MEDIA_BUS_FMT_VYYUYY8_1X24:
        case MEDIA_BUS_FMT_VYYUYY10_4X20:
-               vid_fmt = XSCD_COLOR_FMT_YUV_420;
+               vid_fmt = XSCD_VID_FMT_YUV_420;
                break;
        case MEDIA_BUS_FMT_UYVY8_1X16:
        case MEDIA_BUS_FMT_UYVY10_1X20:
-               vid_fmt = XSCD_COLOR_FMT_YUV_422;
+               vid_fmt = XSCD_VID_FMT_YUV_422;
                break;
        case MEDIA_BUS_FMT_VUY8_1X24:
        case MEDIA_BUS_FMT_VUY10_1X30:
-               vid_fmt = XSCD_COLOR_FMT_YUV_444;
+               vid_fmt = XSCD_VID_FMT_YUV_444;
                break;
        case MEDIA_BUS_FMT_RBG888_1X24:
        case MEDIA_BUS_FMT_RBG101010_1X30:
-               vid_fmt = XSCD_COLOR_FMT_RGB;
+               vid_fmt = XSCD_VID_FMT_RGB;
                break;
        default:
-               vid_fmt = XSCD_COLOR_FMT_YUV_420;
+               vid_fmt = XSCD_VID_FMT_YUV_420;
        }
 
        return vid_fmt;
@@ -227,7 +210,7 @@ static int xscd_s_stream(struct v4l2_subdev *subdev, int enable)
        spin_lock_irqsave(&chan->dmachan.lock, flags);
 
        if (shared_data->memory_based) {
-               chan_offset = chan->id * XILINX_XSCD_CHAN_OFFSET;
+               chan_offset = chan->id * XSCD_CHAN_OFFSET;
                xscd_chan_configure_params(chan, shared_data, chan_offset);
                if (enable) {
                        if (!shared_data->active_streams) {
@@ -347,7 +330,7 @@ static void xscd_event_notify(struct xscd_chan *chan)
        u32 sad, scd_threshold;
 
        sad = xscd_read(chan->iomem, XSCD_SAD_OFFSET +
-                       (chan->id * XILINX_XSCD_CHAN_OFFSET));
+                       (chan->id * XSCD_CHAN_OFFSET));
        sad = (sad * XSCD_V_SUBSAMPLING * MULTIPLICATION_FACTOR) /
               (chan->format.width * chan->format.height);
        eventdata = (u32 *)&chan->event.u.data;

diff --git a/drivers/media/platform/xilinx/xilinx-scenechange-dma.c b/drivers/media/platform/xilinx/xilinx-scenechange-dma.c
index bbb588ec405d3f62ddfd2bd7247186130a91eec5..8f59d941e6162e4ed69bf6a88a2881bac2b9e4f0 100644 (file)
--- a/drivers/media/platform/xilinx/xilinx-scenechange-dma.c
+++ b/drivers/media/platform/xilinx/xilinx-scenechange-dma.c
@@ -26,22 +26,6 @@
 
 #include "xilinx-scenechange.h"
 
-/* SCD Registers */
-/* Register/Descriptor Offsets */
-#define XILINX_XSCD_CTRL_OFFSET                0x00
-#define XILINX_XSCD_GIE_OFFSET         0x04
-#define XILINX_XSCD_IE_OFFSET          0x08
-#define XILINX_XSCD_ADDR_OFFSET                0x40
-#define XILINX_XSCD_CHAN_EN_OFFSET     0x780
-
-/* Control Registers */
-#define XILINX_XSCD_CTRL_AP_START      BIT(0)
-#define XILINX_XSCD_CTRL_AP_DONE       BIT(1)
-#define XILINX_XSCD_CTRL_AP_IDLE       BIT(2)
-#define XILINX_XSCD_CTRL_AP_READY      BIT(3)
-#define XILINX_XSCD_CTRL_AUTO_RESTART  BIT(7)
-#define XILINX_XSCD_GIE_EN             BIT(0)
-
 /**
  * struct xscd_dma_device - Scene Change DMA device
  * @regs: I/O mapped base address
@@ -156,7 +140,7 @@ dma_cookie_t xscd_dma_tx_submit(struct dma_async_tx_descriptor *tx)
  */
 void xscd_dma_chan_enable(struct xscd_dma_chan *chan, int chan_en)
 {
-       xscd_write(chan->iomem, XILINX_XSCD_CHAN_EN_OFFSET, chan_en);
+       xscd_write(chan->iomem, XSCD_CHAN_EN_OFFSET, chan_en);
 }
 
 /**
@@ -180,7 +164,7 @@ static void xscd_dma_complete_descriptor(struct xscd_dma_chan *chan)
 void xscd_dma_start_transfer(struct xscd_dma_chan *chan)
 {
        struct xscd_dma_tx_descriptor *desc;
-       u32 chanoffset = chan->id * XILINX_XSCD_CHAN_OFFSET;
+       u32 chanoffset = chan->id * XSCD_CHAN_OFFSET;
 
        if (!chan->en)
                return;
@@ -205,7 +189,7 @@ void xscd_dma_start_transfer(struct xscd_dma_chan *chan)
                                struct xscd_dma_tx_descriptor, node);
 
        /* Start the transfer */
-       xscd_write(chan->iomem, XILINX_XSCD_ADDR_OFFSET + chanoffset,
+       xscd_write(chan->iomem, XSCD_ADDR_OFFSET + chanoffset,
                   desc->sw.luma_plane_addr);
 
        list_del(&desc->node);
@@ -396,13 +380,11 @@ void xscd_dma_halt(struct xscd_dma_chan *chan)
        struct xscd_dma_device *xdev = chan->xdev;
 
        if (xdev->memory_based)
-               xscd_clr(chan->iomem, XILINX_XSCD_CTRL_OFFSET,
-                        XILINX_XSCD_CTRL_AP_START);
+               xscd_clr(chan->iomem, XSCD_CTRL_OFFSET, XSCD_CTRL_AP_START);
        else
                /* Streaming based */
-               xscd_clr(chan->iomem, XILINX_XSCD_CTRL_OFFSET,
-                        XILINX_XSCD_CTRL_AP_START |
-                        XILINX_XSCD_CTRL_AUTO_RESTART);
+               xscd_clr(chan->iomem, XSCD_CTRL_OFFSET,
+                        XSCD_CTRL_AP_START | XSCD_CTRL_AUTO_RESTART);
 
        chan->idle = true;
 }
@@ -416,13 +398,11 @@ void xscd_dma_start(struct xscd_dma_chan *chan)
        struct xscd_dma_device *xdev = chan->xdev;
 
        if (xdev->memory_based)
-               xscd_set(chan->iomem, XILINX_XSCD_CTRL_OFFSET,
-                        XILINX_XSCD_CTRL_AP_START);
+               xscd_set(chan->iomem, XSCD_CTRL_OFFSET, XSCD_CTRL_AP_START);
        else
                /* Streaming based */
-               xscd_set(chan->iomem, XILINX_XSCD_CTRL_OFFSET,
-                        XILINX_XSCD_CTRL_AP_START |
-                        XILINX_XSCD_CTRL_AUTO_RESTART);
+               xscd_set(chan->iomem, XSCD_CTRL_OFFSET,
+                        XSCD_CTRL_AP_START | XSCD_CTRL_AUTO_RESTART);
 
        chan->idle = false;
 }
@@ -433,8 +413,8 @@ void xscd_dma_start(struct xscd_dma_chan *chan)
  */
 void xscd_dma_reset(struct xscd_dma_chan *chan)
 {
-       xscd_write(chan->iomem, XILINX_XSCD_IE_OFFSET, XILINX_XSCD_IE_AP_DONE);
-       xscd_write(chan->iomem, XILINX_XSCD_GIE_OFFSET, XILINX_XSCD_GIE_EN);
+       xscd_write(chan->iomem, XSCD_IE_OFFSET, XSCD_IE_AP_DONE);
+       xscd_write(chan->iomem, XSCD_GIE_OFFSET, XSCD_GIE_EN);
 }
 
 /**

diff --git a/drivers/media/platform/xilinx/xilinx-scenechange.c b/drivers/media/platform/xilinx/xilinx-scenechange.c
index c07b9e6d568d5a32c7174ab9e3ddd07d016211e3..5f8b7acad5918c276af00789ebdbfde03793c615 100644 (file)
--- a/drivers/media/platform/xilinx/xilinx-scenechange.c
+++ b/drivers/media/platform/xilinx/xilinx-scenechange.c
@@ -18,11 +18,11 @@ static irqreturn_t xscd_irq_handler(int irq, void *data)
        struct xscd_device *xscd = (struct xscd_device *)data;
        u32 status;
 
-       status = xscd_read(xscd->iomem, XILINX_XSCD_ISR_OFFSET);
-       if (!(status & XILINX_XSCD_IE_AP_DONE))
+       status = xscd_read(xscd->iomem, XSCD_ISR_OFFSET);
+       if (!(status & XSCD_IE_AP_DONE))
                return IRQ_NONE;
 
-       xscd_write(xscd->iomem, XILINX_XSCD_ISR_OFFSET, XILINX_XSCD_IE_AP_DONE);
+       xscd_write(xscd->iomem, XSCD_ISR_OFFSET, XSCD_IE_AP_DONE);
        return IRQ_HANDLED;
 }
 

diff --git a/drivers/media/platform/xilinx/xilinx-scenechange.h b/drivers/media/platform/xilinx/xilinx-scenechange.h
index 72c6fc410ed3777598c911c281bc08099a6448e7..b03dc925944c385eb3095ebaafcb4d71e58f5d00 100644 (file)
--- a/drivers/media/platform/xilinx/xilinx-scenechange.h
+++ b/drivers/media/platform/xilinx/xilinx-scenechange.h
@@ -30,12 +30,37 @@
 #include "../../../dma/dmaengine.h"
 
 /* Register/Descriptor Offsets */
-#define XILINX_XSCD_ISR_OFFSET         0x0c
-#define XILINX_XSCD_CHAN_OFFSET                0x100
-
-/* Interrupt Status and Control */
-#define XILINX_XSCD_IE_AP_DONE         BIT(0)
-#define XILINX_XSCD_IE_AP_READY                BIT(1)
+#define XSCD_CTRL_OFFSET               0x000
+#define XSCD_CTRL_AP_START             BIT(0)
+#define XSCD_CTRL_AP_DONE              BIT(1)
+#define XSCD_CTRL_AP_IDLE              BIT(2)
+#define XSCD_CTRL_AP_READY             BIT(3)
+#define XSCD_CTRL_AUTO_RESTART         BIT(7)
+
+#define XSCD_GIE_OFFSET                        0x004
+#define XSCD_GIE_EN                    BIT(0)
+
+#define XSCD_IE_OFFSET                 0x008
+#define XSCD_IE_AP_DONE                        BIT(0)
+#define XSCD_IE_AP_READY               BIT(1)
+
+#define XSCD_ISR_OFFSET                        0x00c
+#define XSCD_WIDTH_OFFSET              0x010
+#define XSCD_HEIGHT_OFFSET             0x018
+#define XSCD_STRIDE_OFFSET             0x020
+#define XSCD_VID_FMT_OFFSET            0x028
+#define XSCD_VID_FMT_RGB               0
+#define XSCD_VID_FMT_YUV_444           1
+#define XSCD_VID_FMT_YUV_422           2
+#define XSCD_VID_FMT_YUV_420           3
+#define XSCD_VID_FMT_Y8                        24
+#define XSCD_VID_FMT_Y10               25
+
+#define XSCD_SUBSAMPLE_OFFSET          0x030
+#define XSCD_SAD_OFFSET                        0x038
+#define XSCD_ADDR_OFFSET               0x040
+#define XSCD_CHAN_OFFSET               0x100
+#define XSCD_CHAN_EN_OFFSET            0x780
 
 #define XSCD_MAX_CHANNELS              8