net: phy: Fix mask value write on gmii2rgmii converter speed register
To clear Speed Selection in MDIO control register(0x10),
ie, clear bits 6 and 13 to zero while keeping other bits same.
Before AND operation,The Mask value has to be perform with bitwise NOT
operation (ie, ~ operator)
This patch clears current speed selection before writing the
new speed settings to gmii2rgmii converter
Following issues are being observed when SMMU is
enabled,
- After suspend/resume with FPD off,all peripherals
registered with SMMU are failed to work.
- SATA device detection is failed
Disabling SMMU till said issues are fixed.
Rajan Vaja [Mon, 28 Aug 2017 09:13:57 +0000 (02:13 -0700)]
ARM64: zynqmp: Do not set requirements to 0 for wakeup sources
Devices which are set as wakeup source or belongs to wakeup
source device's path should not be powered off by generic power
domain driver.
Add check in zynqmp GPD power off function to check if device
is in wakeup source path. If so, set capabilities to WAKEUP
instead of 0 in GPD power off function.
Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Fix issues with vdma mulit fstore configuration
This commit
ie: 'commit 4f143cb03aba ("dmaeninge: xilinx_dma: Fix bug in multiple
frame stores scenario in vdma")'
fixes issues with multiple fstore by using circular mode feature.
This implementation has a limitation as user needs to enable a hidden
configuration option(c_debug_all) in the IP while creating the design.
If user not aware of this h/w option and submits more frames
then driver throughs a warning asking to enable the
hidden configuration option.
This patches fixes these issues by using the park mode feature.
With this patch driver continuously parks through frame buffers
based on the number of frames user submitted.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Some monitors require delay to fully wake up. Otherwise, it may
result in some error such as training failure.
Delay of 4 msec was not specified in the spec, but found from
experimentation (ex, no failure for 20 times or more). Thus,
this setting is exposed as module parameter so that user can
change if needed.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dma: xilinx: Add private API to permit retrieval of supported mem formats
The video Framebuffer DMA IP requires clients to send a fourcc code
to indicate the memory format layout. The IP can be configured to support
a variety of memory formats ranging from YUYV, RGB and in either 8 bit
or 10 bit formats. There has been no method for clients to obtain
this list of supported formats. This patch adds private APIs that
can be called from clients to retrieve this list so that user space
applications can choose from any of the available memory formats.
Depends on patch 13fd162 (dma: xilinx: Bug fix to ensure only video formats
enabled in IP are in driver)
Hyun Kwon [Wed, 30 Aug 2017 22:05:44 +0000 (15:05 -0700)]
drm: xilinx: dp: Enable the training pattern transmission early
Per DP v1.2 spec 3.5.1.2.2, the transmission of training pattern
needs to be enabled before setting the sink device. This sequence
was causing the failure of initial training attempt, thus, enable
the pattern in the controller before setting the sink through aux.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Wed, 30 Aug 2017 06:34:16 +0000 (12:04 +0530)]
zynq: devicetree: Remove 'broken-adma2' property
This patch removes 'broken-adma2' property from the zynq device-tree.
This basically enables the use of ADMA instead of SDMA. With the latest
kernel the ADMA is working fine in SD so no need to use the SDMA which
is slower than ADMA.
Fixed by : 7c415150cdd6 ("ARM: zynq: Reserve correct amount of non-DMA RAM")
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeffrey Mouroux [Tue, 29 Aug 2017 01:12:45 +0000 (18:12 -0700)]
dma: xilinx: Bug fix to ensure GPIO is reset between DMA operations
Some registers within the Video Framebuffer driver, such as the
video format register, require a reset of the IP before they can
be altered. Because there is no software accessible reset register,
an external GPIO is used. This patch fixes a runtime issue wherein
clients wish to reprogram the IP for a new memory between DMA operations.
Without this fix, the Video Framebuffer Write IP may halt when a client
requests a new DMA operation using a different memory format for
writes to host memory. In some cases, Framebuffer Read operations
will need to be reset when the downstream video pipeline is being
reset.
Saurabh Sengar [Tue, 29 Aug 2017 06:32:57 +0000 (12:02 +0530)]
drm: sdi: xilinx: correcting multi link payload value
Channel bit have to be set only in case of multi link data.
In SDI-TX logicore IP, except 3GB mode all other modes are
single link only, hence these bit is redundant.
3GB mode is dual link.
For 3GB mode first link have to be programmed as channel 1,
and second link payload have to be programmed as channel 3.
Mubin Sayyed [Thu, 31 Aug 2017 05:56:06 +0000 (11:26 +0530)]
arm64: zynqmp: Add back stream-id-cells property for lpd-dma
stream-id-cells property is mandatory for SMMU driver over xen,
so adding it back to all lpd-dma-channels.
Since just removing "iommus" property suffice to bypass SMMU over
native linux,SMMU would be still bypassed for lpd-dma over linux.
Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drm: xilinx: plane: Don't cache the property values
Some of these properties need to be updated as hardware values
don't get restored to the default values. Thus, don't cache
the values, but update those when there's request.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The present logic doesn't fetch the correct parent node when two usb nodes
are enabled. It searches all nodes and doesn't fetch the first node with
matching compatible string when two usb nodes are enabled.
This patch fixes the logic by searching "xlnx,zynqmp-dwc3" compatible
string only in the parent nodes instead of the searching all nodes.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: qspi: Corrected the sequence for accessing flash part
For accessing flash part using the mtd devices for architectures which
only supports 3 byte addressing need to call write_ear() for accessing
memory above 16MB. After every call to write_ear(), write_enable()
has to be called for further process.
Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeffrey Mouroux [Mon, 28 Aug 2017 21:56:54 +0000 (14:56 -0700)]
Bug fix to ensure only video formats enabled in IP are in driver
The driver used to assume that all IP supported video formats were
legal choices for configuration. However, the IP can be configured
to support all or only some (or only one) of the many possible formats.
This patch adds the needed mechanism via device-tree to communicate to
the driver which video formats are actually supported in the IP.
Additional changes are required to ensure that DMA client requests
for video formats that are NOT supported by the device instance are
rejected.
Jeffrey Mouroux [Mon, 28 Aug 2017 21:56:53 +0000 (14:56 -0700)]
Documentation: devicetree: bindings: dma: New dts property
A new device tree property is described that will describe
the video formats supported in the Video Framebuffer DMA device.
The Video Framebuffer IP is configurabe and can be configured with
varying support for a number of possible video memory formats in
an effort to tailor the size of the logic footprint. The driver
will utilize this new device tree property to describe this
configuration.
Jeffrey Mouroux [Mon, 28 Aug 2017 21:56:52 +0000 (14:56 -0700)]
dma: xilinx: Update to Framebuffer Driver to support dual addr pointers
The 2017.3 version of the Video Framebuffer supports a separate address
pointer for the chroma plane. This is needed when the chroma plane
is not contiguous with the luma plane for semi-planar formats. This
patch updates the client API as well. Additionally, the IP can be
configured for either 32-bit or 64-bit DMA address pointers. A
new device tree property is added which is used to indicate the address
width and a callback is set during probe to write to memory using
either 32-bit or 64-bit address formats depending on this dts property
as well as the size of dma address space supported on the host.
Jeffrey Mouroux [Mon, 28 Aug 2017 21:56:51 +0000 (14:56 -0700)]
Documentation: bindings: devicetree: dma: New compatible string and prop
The Video Framebuffer driver will remove support for any v1 IP. The
compatibility string associated with the v1 IP is described and the lack
of future support indicated in the device tree bindings document.
Additionally, for the v2 IP, the Video Framebuffer IP now supports either
32-bit or 64-bit dma address pointers which is indicated with a new
required property.
Mousumi Jana [Mon, 28 Aug 2017 08:25:09 +0000 (13:55 +0530)]
can: xilinx: fix runtime power management code
This patch adds the fix for runtime power management.
Without this the device usage counter decremented and device
is going to suspend state.This patch resumes the device and
prevents it from being suspended again.
Signed-off-by: Mousumi Jana <mousumij@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vishal Sagar [Mon, 28 Aug 2017 06:06:12 +0000 (11:36 +0530)]
v4l: xilinx: sdirxss: Get EDH status only in case of SD mode
The EDH status registers are applicable only in SD mode.
So EDH status related V4L controls check for current mode to be SD mode
before accessing EDH status.
Vishal Sagar [Mon, 28 Aug 2017 06:06:10 +0000 (11:36 +0530)]
v4l: xilinx: sdirxss: Detect mode based on capability
Set the mode detection based on IP configuration.
If the IP is configured for 3G mode then don't allow detection for
6G and 12G Integral/Fractional modes.
If the IP is configured for 6G mode then don't allow detection for 12G
Integral/Fractional modes.
Vishal Sagar [Mon, 28 Aug 2017 06:06:08 +0000 (11:36 +0530)]
v4l: xilinx: sdirxss: Update for new register spec
This patch adds support in driver for new register spec finalized for
SDI Rx Subsystem in 2017.3.
Some bits from old registers are moved to new ones modifying the bit masks.
Some old registers offsets have changed.
Interrupt status register now has standard W1C behavior.
Overflow/underflow interrupts are added.
So removing V4L control and added events.
Global interrupt enable register added.
Soft reset bit is added to Reset Control Register.
CRC Error Count register 31-16 exchanged with 15-0 with W1C behaviour.
Leon Luo [Fri, 25 Aug 2017 19:56:16 +0000 (12:56 -0700)]
media: imx274 V4l2 driver for Sony imx274 CMOS sensor
The imx274 is a Sony CMOS image sensor that has 1/2.5 image size.
It supports up to 3840x2160 (4K) 60fps, 1080p 120fps. The interface
is 4-lane MIPI running at 1.44Gbps each.
This driver has been tested on Xilinx ZCU102 platform with a Leopard
LI-IMX274MIPI-FMC camera board.
Support for the following features:
-Resolutions: 3840x2160, 1920x1080, 1280x720
-Frame rate: 3840x2160 : 5 – 60fps
1920x1080 : 5 – 120fps
1280x720 : 5 – 120fps
-Exposure time: 16 – (frame interval) micro-seconds
-Gain: 1x - 180x
-VFLIP: enable/disable
-Test pattern: 12 test patterns
Signed-off-by: Leon Luo <leonl@leopardimaging.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Leon Luo [Fri, 25 Aug 2017 19:56:17 +0000 (12:56 -0700)]
dt: bindings: media: Add dt binding for imx274
The binding file for imx274 CMOS sensor V4l2 driver
Signed-off-by: Leon Luo <leonl@leopardimaging.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
When registering the rtc device to be used to handle alarm timers,
get_device is used to ensure the device doesn't go away but the module can
still be unloaded. Call try_module_get to ensure the rtc driver will not go
away.
Reported-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
During the calibration process ICM_CFG register should be set to any
valid lane. The previous version was using hardcoded setting of PCIe
for lane 2 and 3. This breaks other devices on these lanes if they
don't configure the phy in Linux (i.e. expect the value to be configured
in FSBL).
Current version will use the ICM_CFG value for the first selected phy
instead of hardcoding lanes 2 and 3 to PCIe.
Signed-off-by: Edgar Lakis <ela@phaseone.com> Acked-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Fri, 18 Aug 2017 01:09:40 +0000 (18:09 -0700)]
drm: xilinx: encoder: Check the encoder init function
Check if the encoder slave driver registered the init callback.
If the callback exists, the encoder driver assumes that
the slave driver is ready to initialize.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Vishal Sagar [Wed, 16 Aug 2017 11:14:06 +0000 (16:44 +0530)]
v4l: xilinx: sdirxss: Add V4L control for Mode detection
Mode detection V4L control added. Modes are passed as bitmask based on
xilinx-sdirxss.h. If only one mode is selected then driver programs IP
in Fixed mode else multi mode detection is enabled.
Vishal Sagar [Wed, 16 Aug 2017 11:14:05 +0000 (16:44 +0530)]
v4l: xilinx: sdirxss: Add V4L control for EDH error count
This patch adds V4L control for enabling EDH counter.
The list of masks for error conditions are added.
It also fixes how the EDH Error counter register is set.
Vishal Sagar [Wed, 16 Aug 2017 11:14:02 +0000 (16:44 +0530)]
v4l: xilinx: sdirxss: Streaming is enabled only on video lock
Enable mode detection and start SDI Rx IP by default. The video bridges
are enabled/disabled when starting/stopping streaming.
Streaming is started only if video is locked.
PCFG_PROG_B is already 1, so asserting it here will not generate
a edge. If the PL is not correctly loaded before (i.e. an invalid bitfile),
waiting for PCFG_INIT will wait forever.
Signed-off-by: Martijn de Gouw <martijn.de.gouw@prodrive-technologies.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: change condition for check request completion
it may be possible that whole reqest not able to fit in trb
availables. since actual length is calculated from trb size
field which suggest how many bytes not able to transfer out
of trb trnafser size. this fix will remove the false
assumption of request completion
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
if queue is full we are depending on HWO bit to see if queue is
full or empty. after advancing trb_enqueue last trb will be the
trb we are working right now. so need to check after HWO bit is
set
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Felipe Balbi [Fri, 11 Aug 2017 08:54:20 +0000 (04:54 -0400)]
usb: dwc3: gadget: always try to prepare on started_list first
In cases where we're given an SG-list which is
longer than the amount of currently available TRBs,
we will be left with the same request on
started_list and we should prioritize that request
over possible new requests on pending_list. That's
a way to guarantee requests complete in order.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
according to databook it may be possible host and device become
out of sync where device wait for host to issue prime transcation
and host waits for device to issue erdy to avoid such deadlock
timeout need to be implement. after timeout device will first
stop transfer and again restart the transfer
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: dwc3: enable transfer complete event for stream endpoint
start transfer for new stream id need to free previously held
transfer resources. transfer complete event will automatically
free up the resource once transfer associated with stream
completes
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: gadget: f_tcm: add TARGET_SCF_ACK_KREF flag in BOT
in BOT mode se_cmd and I/O resource getting free during target
fabric module operation check_stop_free which does not gauranteed
freeing of resource after actual usb bus transfer. adding
TARGET_SCF_ACK_KREF flag during submitting target request will
increment additinal cmd_kref which will prevent deallocating
se_cmd and I/O resource before actual usb bus transfer.
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
increase in performance can be achived by queueing multiple command
request during super speed uas mode. this will make a best use of
uas and stream support.
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: gadget: f_tcm: comp_descriptor workaround during SS gadget
If device connect in SS then comp_descriptor with stream
should be atteched to descriptor. Since BOT and UAS using
same endpoint, config_ep_by_speed will returns first match
with comp_descriptor without stream. This is just workaround
proper fix need to be introduced.
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
usb: gadget: f_tcm: adjust write length with max packet size
transfer size on out endpoint should be in multiple of endpoint
max packet size. this patch will adjust transfer size on out endpint
with multiple of max packet size
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 4 Aug 2017 07:34:55 +0000 (09:34 +0200)]
watchdog: cadence_wdt: Show information when driver is probed
Showing message that driver is loaded is common across drivers.
This change also fixes checkpatch (--strict) warning
"Alignment should match open parenthesis".
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Thu, 10 Aug 2017 08:22:03 +0000 (13:52 +0530)]
zynqmp: sdhci: Prevent SD driver deferred probe after host init
This patch prevents deferred probe after the host initialization is
done. Instead if the deferred probe is necessary, do it before the host
initialization. This way the unnecessary increase in host id can be
avoided.
In standard boot flow deferred probe is called at least 2 times
that's why it is better to extract it out.
Also add error message when getting silicon version fails.
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rohit Athavale [Fri, 11 Aug 2017 01:03:54 +0000 (18:03 -0700)]
v4l: xilinx-vpss-scaler: fix dev_dbg logging typo and remove dead code
This commit corrects the dev_dbg typo in the xilinx vpss scaler driver.
It also removes deadcode from xv_hscaler_setup_video_fmt() as
xv_vscaler_setup_fmt() cannot return XVIDC_CSF_YCRCB_420.
Hyun Kwon [Thu, 10 Aug 2017 18:26:10 +0000 (11:26 -0700)]
drm: xilinx: fb: Fix styles
Fix checkpatch warnings such as alignement and extra blank lines:
CHECK: Alignment should match open parenthesis
+ DRM_DEBUG_KMS("surface width(%d), height(%d) and bpp(%d)\n",
+ sizes->surface_width, sizes->surface_height,
CHECK: Blank lines aren't necessary before a close brace '}'
+
+ }
CHECK: Please don't use multiple blank lines
+
+
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>