dmaengine: xilinx: dma: Program hardware supported buffer length

AXI-DMA IP supports configurable (c_sg_length_width) buffer length
register width, hence read buffer length (xlnx,sg-length-width) DT
property and ensure that driver doesn't program buffer length
exceeding the supported limit. For VDMA and CDMA there is no change.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: DT: dma: Add axi-dma buffer length property

Buffer length is an optional DMA node property. DMA driver will
uses this property to ensure that programmed DMA length doesn't
exceed IP supported buffer length(c_sg_length_width).

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dma: Add support for XV15 and XV20 contiguous formats

This patch updates the framebuffer driver to add support for
XV15 and XV20 contiguous formats.

Signed-off-by: Devarsh Thakkar <devarsht@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: devicetree: bindings: dma: Update fourcc codes for xv15/20

Support for xv15 and xv20 formats have been added to the Xilinx video
framebuffer driver.

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: vsagar@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l2-core: Update entries for XV15 and XV20 contiguous formats

This patch adds missing entries XV20 and XV15 contiguous formats
and fix the warning as format description size is going beyond
32 byte limit.

Signed-off-by: Devarsh Thakkar <devarsht@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Add XV15 and XV20 contiguous format support

This patch adds support for XV15 and XV20 contiguous formats
support. Updated with right bitsperpixel for YUV 422 format.

Signed-off-by: Devarsh Thakkar <devarsht@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dt-bindings: clock: zynqmp: Correct clock names

Some clocks names were intentionally kept incorrect to
match with Linux clock names for backward compatibility.
As now, clock is complete new driver, this is not required
so use proper names for the clocks.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Acked-by: Jolly Shah <jollys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

gpio: xilinx: Add reset support

This patch updates xlate api and gpio cells value to
provide reset support for other IP's using axi gpio.

Signed-off-by: Swapna Manupati <swapnam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dt-bindings: gpio-xilinx: Update gpio-cells information

This patch adds extra cell for flags in gpio-cells to reset
other IP's using axi gpio.

Signed-off-by: Swapna Manupati <swapnam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

usb: dwc3: otg: don't clear event buffers when changing to Host mode from Device mode

Clearing event buffers when changing from Device mode -> Host mode
may require allocating event buffers again during role swap from
Host mode -> Device mode. Changing the event buffers at runtime are
not triggering events in device mode and also the role swap can happen
at any time. So, better not to clear the event buffers during role
swap instead reuse the previously allocated event buffers.
This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm: zynq: pl310_edac_l2: Update header file

Changed the header file from edac_core.h, which no
longer exists, to edac_module.h.

Signed-off-by: Jordan Anderson <anderson.jordan59@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: reset the mixer IP before programming

Resetting the HLS IP as soon as gpio driver is probed.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: remove deprecated dmaengine_terminate_all

Replacing dmaengine_terminate_all with dmaengine_terminate_sync,
as the former one is deprecated.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dt: bindings: media: xilinx: Remove unimplemented TPG compatible string

TPG compatible string "xlnx,v-tpg-6.0" is not supported in the driver.
Hence remove unimplemented compatible string.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

media: xilinx: vip: Correct the fourcc code for BGRX8 format.

Correct the V4L2_PIX_FMT fourcc code for BGRX8 format
to V4L2_PIX_FMT_XBGR32.

Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dma: xilinx: Correct the V4L fourcc for BGRX8 in framebuffer driver

Correct the V4L2_PIX_FMT fourcc code for BGRX8 to V4L2_PIX_FMT_XBGR32.

Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: devicetree: bindings: dma: Correct the BGRX8 format fourcc code

The BGRX8 framebuffer format is corrected for V4L2 Fourcc by changing
V4L2_PIX_FMT_XRGB32 to V4L2_PIX_FMT_XBGR32 in the table.

Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: Add BGR color format support.

Add support for the new BGR color format supported by Framebuffer
driver.

Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dma: xilinx: Add support for BGR8 color format in Framebuffer

Add support for BGR8 color format (Blue in LSB, 8 bits per component)
in Framebuffer.

Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: devicetree: bindings: dma: Add support for BGR8 color format

Add support for BGR8 color format (Blue in LSB, 8 bits per component)
to the Xilinx Video Framebuffer driver.

Signed-off-by: Vishal Sagar <vsagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Fix bytes per line calculation

In current implementation there is a bug where min_bpl value
is not satisfying dma alignment. This patch will fix the issue
by aligning the value properly.

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Handle 10 bit format calucations for XV20

This patch handle 10 bit calculations for YUV 422 10 bit format

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Fix sizeimage calculation

sizeimage should be calculated using bytesperline instead
of width

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

media: v4l2-core: Update V4L2 framework with new fourcc codes

New fourcc codes have been added to support additional video
memory layout supported by Xilinx Video IP.  These have been
added to the V4L2 framework with this patch.

Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: sdirxss: Add support for YUV420 decoding

Add support for YUV420 10bpc decoding from the ST352 payload.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dt: bindings: media: xilinx: Add YUV420 decoding support in UHDSDI Rx

Updates the documentation for supporting YUV420 10bpc
in UHDSDI Rx Subsystem driver.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: sdi: Adding yuv 420 support

Adding YUV 420 10 bit color format support for SDI Tx

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-tpg: Add YUV 420 media bus format support to TPG driver

This patch updates the TPG IP driver to add support for the newly
created YUV 420 bus format.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

net: xilinx: axiethernet: Add USXGMII support

This patch adds support for USXGMII IP in axiethernet driver.
This IP has a MAC similar to 10G/25G IP and supports USXGMII phy protocol.
USXGMII phy supports speeds from 10Mbps to 10Gbps. Only one phy speed
can be advertised at a time and this choice is obtained from the user
via a devicetree property. This patch was tested at 1G and 2.5G speeds.
Since the MAC functionality is similar to 10G/25G, the same mac type is
used in the config structure. USXGMII IP requires a GT reset and this is
added to axienet_device_reset with a check based on mac type.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

devicetree: Update documentation for USXGMII

Update USXGMII compatible string and optional properties.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: zynqmp: config: Enable soft IP DRM drivers

This enables DSI, SDI, Mixer, and the PL display drivers in defconfig.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Acked-by: Saurabh Sengar <saurabhs@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: zynqmp: dt: Add new ZynqMP DP changes

This removes old dt contents from all dts files for ZynqMP DisplayPort
and updates all with new bindings. Please note, some of these changes
are only build-tested.

The DP includes an i2c interface for ddc communication.
drm_dp_aux_register() registers an i2c adapter for it. The function
walks through child nodes of the device node ( = dp node) and tries to
register child nodes as i2c device. This ends up giving bunch or error
messages saying child nodes are not compatible with i2c device bindings
(in of_i2c_register_device()). That's why i2c dummy node was added to
make it clear there's no i2c child device and avoid such error messages.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: zynqmp: config: Enable new Xilinx drm configs

Enable the new DRM configs and deprecate old ones.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Fixing wrong stride alignment

Stride alignment must be 8 X pixels_per_clock value.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

net: emaclite: Add 'maxlen' description

Add 'maxlen' description. Fixes kernel-doc warning.

drivers/net/ethernet/xilinx/xilinx_emaclite.c:381:
warning: No description found for parameter 'maxlen'

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

net: emaclite: Remove obsolete else

Remove else as it is not required with if doing a return.
Fixes below checkpatch warning.

WARNING: else is not generally useful after a break or return

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

net: emaclite: Balance braces in else statement

Add braces to else statements to comply with Linux kernel
coding style' and avoid the following checkpatch message:

'CHECK: Unbalanced braces around else statement'

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

net: emaclite: Use __func__ instead of hardcoded name

Switch hardcoded function name with a reference to __func__ making
the code more maintainable. Address below checkpatch warning:

WARNING: Prefer using '"%s...", __func__' to using 'xemaclite_mdio_read',
this function's name, in a string
+ "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",

WARNING: Prefer using '"%s...", __func__' to using 'xemaclite_mdio_write',
this function's name, in a string
+ "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n"

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

net: emaclite: Fix line over 80 characters

Fix below line over 80 characters checkpatch warning.

WARNING: line over 80 characters
167: FILE: drivers/net/ethernet/xilinx/xilinx_emaclite.c:167:
170: FILE: drivers/net/ethernet/xilinx/xilinx_emaclite.c:170:
185: FILE: drivers/net/ethernet/xilinx/xilinx_emaclite.c:185:
482: FILE: drivers/net/ethernet/xilinx/xilinx_emaclite.c:482:
675: FILE: drivers/net/ethernet/xilinx/xilinx_emaclite.c:675:

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

device-tree: serdes: Remove unused lpd register address mapping

This patch removes the unused lpd register address mapping from
serdes dts node.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

phy: zynqmp: Use eemi framework for performing ULPI reset sequence

This patch modifies the phy-zynqmp.c driver to use eemi framework
for performing ULPI reset sequence.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

zynqmp: firmware: Add IOCTL enum for performing ULPI reset

This patch adds IOCTL_ULPI_RESET IOCTL enum value that is
passed to eemi framework for performing ULPI reset

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dt-bindings: phy: Fix typo in phy-zynqmp binding doc

Issue was reported by checkpatch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Correcting loop termination condition

The layer id starts from 0 and max id should be one less then total count.
The loop was iterating till mixer->layer_cnt, so correcting it to one less.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

crypto: zynqmp: Use new firmware ops

ZynqMP firmware interface driver has been replaced
with new firmware driver. Use new firmware ops
instead of old firmware APIs in crypto drivers.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Acked-by: Jolly Shah <jollys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

usb: xhci: wait for atleast 1ms after exiting U3

XHCI controller may not properly send LFPS.U3_EXIT signalling after
resuming from suspend(D3->D0). To avoid this, lets wait for atleast
1ms after updating the PORTSC_30.PLS to enter U0 from U3. This patch
does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: zynqmp: Remove ep108 board

ZynqMP Emulation board is no longer tested and there is no reason to
keep maintaining it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

vdmatest: xilinx: Use octal permissions '0444'

Fixed following checkpatch warning
WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider
using octal permissions '0444'.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

vdmatest: xilinx: Fix VDMA hang reported in certain resolutions

Avoid enabling circular_park mode for S2MM as it might happen that engine
continuously circles through frame buffers w/o being programmed and lead
to an undesired hang. In loopback it is recommended to use same park mode
configuration for both channels.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

vdmatest: xilinx: Add hsize and vsize module parameter

Make the horizontal and vertical length configurable. This allows
VDMA IP to be validated for all supported resolution.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>
Acked-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Adding more colors in supported list

Adding more colors in mixer's sanity table of color list

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Adding 10 bit color support

Adding 10 bit color format support

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Adding mixer 3.0 IP support

Adding mixer 3.0 IP support, this adds one extra overlay layer
ie 8th layer.
Also the logo enable bit is moved to 15th from 8, as 8th bit is
now for 8th newly added layer

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dt-bindings: display: xlnx: Modifing mixer compatible string

Adding IP version name in compatible string.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: zynqmp: Add the devicetree node for ocm apm node

Add the dt node for ocm apm.
Disable this IP on ep108 because it wasn't tested there.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

fpga: zynqmp: Remove useless blank line in zynqmp_fpga_remove

It removes checkpatch warning.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

fpga: zynqmp: sync driver with xilfpga library enhancements

From 4.0 xilfpga library version onwards it's not required
to strip the Headers for Both Secure and Non-Secure
Bitstream Images created by bootgen.The entry point
interface inside the xilfpga library is changed as follows.
u32 XFpga_PL_BitSream_Load (UINTPTR WrAddr,
UINTPTR KeyAddr, u32 flags);

So the user need not to pass the Size and IV info to the FW.
The FW will collect those parameters from the Image Headers.

Old bootgen command:
 bootgen -image bistream.bif -arch ZynqMP -process_bitstream bin
 (stripping the Headers).

New bootgen command(2018.1 bootgen):
 bootgen -image bitstream.bif -arch zynqmp  -o Bitstream.bin
 (Without stripping the Headers).

These xilfpga changes are included in PMUFW 1.0 which is required for
running the kernel anyway.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

dma: xilinx: Update Framebuffer Driver with support for new 8-bit/10-bit formats

New DRM and V4L2 fourcc codes have been added to the driver
table. Some of these codes are novel and not yet fully
reviewed nor accepted by the respective communities.

Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: devicetree: bindings: dma: Update for new fourcc code support

Support for more pixel memory formats has been added to the Xilinx Video
Framebuffer driver.

Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-vpss-csc: Support for any-to-any color space converison

With this commit the driver supports RGB, YUV 444, YUV 422 and
YUV 420 media bus formats. This commit also updates the VPSS CSC
color controls for any-to-any conversion. VPSS CSC requires
coefficients to be brought into an RGB style of coefficients
before color controls can be applied and thus shadow coefficients
are used to track the color controls.

This commit extracts the color depth information from the
DT and uses it configuring the clip max and contrast. This
commit also allows the user to specify 8-bit or 10-bit color
depth via the DT.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: media: Update dt-bindings doc for 10-bit color depth in vpss-csc

Add documentation stating support for 10 bit depth for vpss-csc.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Documentation: media: Correct dt-bindings doc for Gamma LUT IP

Correct the IP name from scaler to Gamma LUT and update for
8 and 10-bit color depths.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-gamma: Fix compile error in debug mode

Variable rb is not declared in DEBUG mode, but is referenced.
This fixes the dev_err logging.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-gamma: Add kernel-doc for xgamma_dev struct

This commit adds kernel doc for xgamma_dev struct

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-gamma: Add 10-bit IP support for Video Gammma IP.

This commit adds 10-bit color depth support to the Xilinx Gamma LUT IP
driver. The driver is re-worked to accept color depth from the DT.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-demosaic: Remove Output Video format register

Remove the redundant register for output video format as the Video
Sensor Demosaic IP can only support output video with RGB format.
Also some typos in logging messages are fixed in this commit.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx-vpss-scaler: Add YUV 420 to VPSS Scaler Driver

This commit adds the YUV 420 media bus format to the
VPSS Scaler Driver.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

firmware: zynqmp: Add sysfs to set shutdown scope

The Linux shutdown functionality implemented via PSCI system_off does
not include an option to set a scope, i.e. which parts of the system to
shut down.

This patch creates sysfs that allows to set the shutdown scope for the
next shutdown request. When the next shutdown is performed, the platform
specific portion of PSCI-system_off can use the chosen shutdown scope.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Stefan Krsmanovic <stefan.krsmanovic@aggios.com>
Acked-by: Will Wong <willw@xilinx.com>
Acked-by: Jolly Shah <jollys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

clk: zynqmp: Allow zero divisor value

Zero divider is valid and default for some of ZynqMP
clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
for the clock is set.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Acked-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: csc: Add YUV420 support

This commit adds the YUV 420 media bus format to color space converter driver.

Signed-off-by: Venkateshwar Rao G <vgannava@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: scaler: Add YUV420 support

This commit adds the YUV 420 media bus format to the VPSS Scaler Driver

Signed-off-by: Venkateshwar Rao G <vgannava@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Get scaling and padding factor to calculate DMA params

Get multiplying factor to calculate bpp especially
in case of 10 bit formats.
Get multiplying factor to calculate padding width

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Add scaling and padding factor functions

scaling_factor function returns multiplying factor to calculate
bytes per component based on color format.
For eg. scaling factor of YUV420 8 bit format is 1
so multiplying factor is 1 (8/8)
scaling factor of YUV420 10 bit format is 1.25 (10/8)

padding_factor function returns multiplying factor to calculate
actual width of video according to color format.
For eg. padding factor of YUV420 8 bit format: 8 bits per 1 component
no padding bits here, so multiplying factor is 1
padding factor of YUV422 10 bit format: 32 bits per 3 components
each component is 10 bit and the factor is 32/30

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Fix v4l2 enumeration callback for multiplanar

This fixes issues with v4l2 enumeration callback with multiplanar
formats due to which supported multiplanar formats were not getting
enumerated when using VIDEO_ENUM_FMT ioctl.

The intention of existing implementation for multiplanar formats was
to save in array and return the subset of all the v4l2 formats
supported by attached dma device and the supported media bus format
and also cache the supported media bus format so that for future calls
if same media bus format is called then the v4l2 pixel formats can be
directly returned from the entries saved in the array.

This is acheived now with below changes :
a. Use V4L2 subdev helper functions to query supported media bus
  format code.
b. Cache the media bus format also for the condition when it is empty
  along with whenever new media bus format is detected.
c. Fix NULL pointer deference error by dynamically allocating
  memory for poss_v4l2_fmts.

Signed-off-by: Devarsh Thakkar <devarsht@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Add multi-planar support

The current v4l driver supports single plane formats. This patch
will add support to handle multi-planar formats. Updated driver
capabilities to multi-planar, where it can handle both single and
multi-planar formats

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

v4l: xilinx: dma: Update video format descriptor

This patch updates video format descriptor to help information
viz., number of planes per color format and chroma sub sampling
factors.

This commit adds the various 8-bit and 10-bit that are supported
to the table queried by drivers.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

uapi: media: New fourcc codes needed by Xilinx Video IP

The Xilinx Video Framebuffer DMA IP supports video memory formats
that are not represented in the current V4L2 fourcc library. This
patch adds those missing fourcc codes. This includes both new
8-bit and 10-bit pixel formats.

Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

media: Add documentation for YUV420 bus format

The code is MEDIA_BUS_FMT_VYYUYY8_1X24

Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

media-bus: uapi: Add YCrCb 420 media bus format

This commit adds a YUV 420 media bus format. Currently, one
doesn't exist. VYYUYY8_1X24 does not describe the way the pixels are
sent over the bus, but is an approximation.

Signed-off-by: Rohit Athavale <rohit.athavale@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

media: Add new dt-bindings/vf_codes for supported formats

This commit adds new entries to the exisiting vf_codes that are used
to describe the media bus formats in the DT bindings. The newly added
8-bit and 10-bit color depth related formats will need these updates.

Signed-off-by: Rohit Athavale <rathaval@xilinx.com>
Signed-off-by: Satish Kumar Nagireddy <satishna@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

usb: dwc3: Correct usb dma mask for making SMMU work in device mode

By default dma_coherent_mask is set to 32 bits, because of this the
virtual address generated by the SMMU is masked to 32 bit width.
Due to this reason, the events generated by the USB DMA are not being
updated to the correct physical address and undefined behaviour is
generated.
This patch corrects the above said problem by reading and setting
the DMA coherent mask based on the GHWPARAMS0.MDWIDTH value.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm: zynq: Add DTs for xilinx platforms

Add device tree descriptions for Xilinx boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arm64: zynqmp: Add DTs for xilinx platforms

Add device tree descriptions for Xilinx boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: pl_disp: Adding semi planar support

Adding semi planar color format support in pl_disp for color aware dma.
Framebuffer driver requires chroma buffer address for semi-planar color
format. As we dont have any separate API call in dmaengine for passing
chroma buffer, we calculate the offset from chroma buffer to luma buffer
and pass it in src_icg along with xt. In framebuffer driver chroma buffer
is calculated based on this offset from luma buffer address.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

soc: xilinx: xlnx_vcu: Provided API to get core clock

Core Clock frequency related information is provided
through the xvcu_get_clock_frequency API.

Signed-off-by: Dhaval Shah <dshah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

usb: dwc3: gadget: Fix PCM1 for ISOC EP with ep->mult less than 3

For isochronous endpoints with ep->mult less than 3, PCM1 value of
trb->size in set incorrectly.
For ep->mult = 2, this is set to 0/-1 and for ep->mult = 1, this is
set to -2. This is because the initial mult is set to ep->mult - 1
instead of 2.

Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

usb: gadget: uvc_video: unlock before submitting a request to ep

There could be chances where the usb_ep_queue() could fail and trigger
complete() handler with error status. In this case, if usb_ep_queue()
is called with lock held and the triggered complete() handler is waiting
for the same lock to be cleared could result in a deadlock situation and
could result in system hang. To aviod this scenerio, call usb_ep_queue()
with lock removed. This patch does the same.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: correcting data type for cursor with and height

Correcting data type to unsigned int from int

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Correcting the cursor width and height

Passing the device tree values to cursor height and width, which was
wrongly set to 0 before.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: Removing dead code

Removing unnecessary loop, assigning plane's layer_data to layer_data
pointer.

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reported-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers: net: ethernet: TSN - Add support in tsn ptp to count tx and rx packets

Add support in tsn ptp to count tx and rx packets

Signed-off-by: Priyadarshini Babu <priyadar@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers: net: ethernet: TSN - Add qbv 256 entries support

Add qbv 256 entries support.

Signed-off-by: Priyadarshini Babu <priyadar@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers: net: ethernet: TSN - Add copy-to-user size fix

Add copy-to-user size fix.

Signed-off-by: Priyadarshini Babu <priyadar@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers: net: ethernet: TSN - Add module header file

Add module header file.

Signed-off-by: Priyadarshini Babu <priyadar@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers: net: ethernet: TSN - Handle qbv get schedule when qbv is disabled

Handle qbv get schedule when qbv is disabled

Signed-off-by: Priyadarshini Babu <priyadar@xilinx.com>
Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

usb: dwc3: Fix the broken suspend/resume functionality in dwc3

Since the GCTL values are lost after suspend, restore the GCTL
prtcap direction values based on the mode of operation. Doing
so, will fix the host/peripheral functionality after resume.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: scaler: Adding Zero out H-phase array before changing resolution

When changing resolutions, the H-phases need to be re-calculated. This
commit zeroes out the H-phase array.

Signed-off-by: Venkateshwar Rao G <vgannava@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: drm_fourcc: Correct the DRM YUV444 10bpc

Correct the DRM format for YUV444 10bpc from XY30 to XV30.

Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: drv: Allow multiple masters on a drm device

This may not be the ideal solution, but is to allow multiple
masters running on a single drm device, when the application
has the admin priviliege. This enables access to master
only resources such as setting drm planes and etc.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drm: xlnx: mixer: logo layer fix

This patch fixes the occasional kernel oops when programing logo layer.
Issue was because of accessing/programing wrong memory.
Following fixes corrected this calculation :
- using the currect buffer b_buf instead of r_buf
- correcting the register address calculation by one offset
- corrected pixel_alpha selection based on color format logic

Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>